System and method for parallel testing of electronic device

A device, comprising:

• a plurality of voltage monitor circuits;
• a non-transitory memory storage comprising instructions;
• and
• a processor in communication with the non-transitory memory storage and the plurality of voltage monitor circuits, wherein the instructions, when executed by the processor cause the processor to:
• determine a subset of voltage monitor circuits having a same targeted threshold voltage,
• set a voltage provided to the subset of voltage monitor circuits from a test voltage supply to the targeted threshold voltage, and
• determine a respective trim code value for each voltage monitor circuit in the subset of voltage monitor circuits by monitoring a change in a logic state at an output of each voltage monitor circuit using a range of trim code values at a monitor reference in each voltage monitor circuit, wherein each trim code is provided from a test data register using a joint test action group (JTAG) interface.

A method for testing voltage monitor circuits in a device, the method comprising:

• programming each voltage monitor circuit to detect an over-voltage or an under-voltage condition of an input voltage using a corresponding targeted threshold voltage;
• raising, from a first voltage to a second voltage, an input voltage to a subset of the voltage monitor circuits, the targeted threshold voltage of each of the subset of the voltage monitor circuits being a voltage between the first voltage and the second voltage;
• monitoring an output of each voltage monitor circuit in the subset of the voltage monitor circuits for a change in a logic state, and based thereon, determining whether a corresponding trim code is properly set for each voltage monitor circuit;
• and
• setting an operating temperature of the voltage monitor circuits to a minimum operating temperature or a maximum operating temperature of the device before raising the input voltage to the subset of the voltage monitor circuits.