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US 12,201,031 B2Granted
Structure and method for MRAM devices having spacer element
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHsiang-Ku Shen, Dian-Hau Chen
Life of this patent
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Abstract
Methods and devices are provided that include a magnetic tunneling junction (MTJ) element. A first spacer layer abuts sidewalls of the MTJ element. The first spacer layer has a low-dielectric constant (low-k) oxide composition. A second spacer layer is disposed on the first spacer layer and has a low-k nitride composition.
Claims20
A semiconductor device, comprising:
- a magnetic tunneling junction (MTJ) element over a semiconductor substrate;
- a top electrode layer over the MTJ element, wherein the top electrode layer is circular in a top view;
- a first spacer layer abutting sidewalls of the MTJ element and encasing the MTJ element such that the first spacer layer has a ring shape in a top view, wherein the first spacer layer has a first low-dielectric constant (low-k) composition;
- a second spacer layer on the first spacer layer, wherein the second spacer layer has a second low-k composition, the second low-k composition different than the first low-k composition;
- and
- an etch stop layer between the first spacer layer and the second spacer layer.
3 more elements
A semiconductor device, comprising:
- a first metallization layer formed over a semiconductor substrate, wherein the first metallization layer has a first portion in a memory region and a second portion in a logic region;
- a memory structure in the memory region including:
- a bottom electrode extending from the first portion of the first metallization layer;
- a first magnetic tunneling junction (MTJ) element on the bottom electrode;
- a top electrode over the MTJ element;
- a first spacer layer abutting sidewalls of the first MTJ element, the bottom electrode, and
- the top electrode, wherein the first spacer layer includes silicon, nitrogen, and is at least one of carbon or boron;
- and
- a second spacer layer on the first spacer layer, wherein the second spacer layer is at least one of silicon, oxygen, and at least one of fluorine or carbon;
- a via structure in the logic region extending from the second portion of the first metallization layer;
- and
- a second metallization layer extending from the via structure, wherein the second metallization layer is coplanar with the MTJ element.
9 more elements
A semiconductor device comprising:
- a first magnetic tunneling junction (MTJ) element over a semiconductor substrate;
- a top electrode layer over the first MTJ element;
- a first spacer layer abutting sidewalls of the first MTJ element and encasing the first MTJ element, wherein the first spacer layer has a first low-dielectric constant (low-k) composition;
- a second spacer layer on the first spacer layer, wherein the second spacer layer has a second low-k composition, wherein the second low-k composition is approximately 15% to approximately 80% lower dielectric constant than the first low-k composition;
- and
- an etch stop layer interposing the first spacer layer and the second spacer layer.
3 more elements
Dependencies are inferred from the claim text.