Memory device including reference bit line for increasing read operation accuracy

A memory device, comprising:

• a plurality of source-drain structure bodies and a plurality of gate structure bodies arranged alternately along a first direction;
• and
• a plurality of global word lines,
• each of the plurality of source-drain structure bodies including
• a bit line extending in a second direction perpendicular to the first direction,
• a first semiconductor layer extending in the second direction, being connected to the bit line, and being of a first conductivity type,
• a second semiconductor layer extending in the second direction, being separated from the first semiconductor layer in a third direction, and being of the first conductivity type, the third direction perpendicular to a plane parallel to the first and second directions, and
• a third semiconductor layer contacting the first and second semiconductor layers and being of a second conductivity type,
• each of the plurality of gate structure bodies including
• a plurality of local word lines arranged in the second direction, each local word line extending in the third direction, and
• a charge storage film provided between the third semiconductor layer and each local word line of the plurality of local word lines,
• wherein a first source-drain structure body of the plurality of source-drain structure bodies includes the bit line forming a first reference bit line;
• and wherein a first global word line of the plurality of global word lines connects to the local word lines in the gate structure bodies of the plurality of gate structure bodies formed on both sides of the first reference bit line and to the local word lines formed in alternate gate structure bodies of the plurality of gate structure bodies that are formed between the remaining plurality of source-drain structure bodies.