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US 12,200,096 B2Granted
Low power edge and data sampling
AssigneeRambus Inc.
InventorJared L. Zerbe
Life of this patent
Estimating the term…
Abstract
An integrated circuit receiver is disclosed comprising a data receiving circuit responsive to a timing signal to detect a data signal and an edge receiving circuit responsive to the timing signal to detect a transition of the data signal. One of the data or edge receiving circuits comprises an integrating receiver circuit while the other of the data or edge sampling circuits comprises a sampling receiver circuit.
Claims20
An integrated circuit (IC) receiver, comprising:
- sampling circuitry to sample data and timing information associated with the data, the data and timing information associated with the data received from an IC transmitter, the sampling circuitry to generate data and edge samples;
- comparison circuitry to compare the data and edge samples to indicate phase error information between the data and the timing information associated with the data;
- a loop interface to transmit an indicator of the phase error information to the IC transmitter to close a feedback loop to adjust a phase relationship between the data and the timing information associated with the data;
- and
- wherein one of the edge samples or the data samples are generated by an integrating sampler, and another of the edge samples or the data samples are generated by a non-integrating sampler.
2 more elements
A method of operation in an integrated circuit (IC) receiver, the method comprising:
- sampling data and timing information associated with the data that is received from an IC transmitter to generate data and edge samples;
- comparing the data and edge samples to indicate phase error information between the data and the timing information associated with the data;
- transmitting an indicator of the phase error information to the IC transmitter via a back-channel interface;
- and
- generating one of the edge samples or the data samples by an integrating sampler;
- and
- generating another of the edge samples or the data samples by a non-integrating sampler.
4 more elements
An integrated circuit (IC) chip, comprising:
- sampling circuitry to sample data and timing information associated with the data, the data and timing information associated with the data received from a second IC chip, the sampling circuitry to generate data and edge samples;
- comparison circuitry to compare the data and edge samples to indicate phase error information between the data and the timing information associated with the data;
- a back-channel interface to transmit an indicator of the phase error information to the second IC chip;
- and
- wherein one of the edge samples or the data samples are generated by an integrating sampler, and another of the edge samples or the data samples generated by a non-integrating sampler.
2 more elements
Dependencies are inferred from the claim text.