Low gate-count and high throughput Reed-Solomon decoding

A memory system, comprising:

• a memory;
• a controller comprising a decoding circuit;
• a host interface configured to receive, from a host device, a request to read data stored in the memory;
• and
• a memory interface coupled to a channel between the memory and the decoding circuit and configured to receive encoded data from the memory via the channel,
• wherein the decoding circuit is configured to decode the encoded data using a Reed-Solomon decoder by detecting and correcting one or more errors in the encoded data to obtain decoded data,
• wherein the detecting and correcting comprises:
• updating Reed-Solomon syndromes based on partial input data of symbols of a Reed-Solomon codeword;
• updating error location polynomial coefficients based on the partial input data;
• maintaining the Reed-Solomon syndromes and the error location polynomial coefficients in the memory prior to starting activation of Reed-Solomon decoding;
• and
• inputting the Reed-Solomon syndromes and the error location polynomial coefficients to a first activation of the Reed-Solomon decoding, the first activation including calculating an initial error evaluator polynomial as a first error evaluator polynomial, performing error detection on the encoded data based on the first error evaluator polynomial to determine presence and location of the one or more errors in an input Reed-Solomon codeword, and updating the error location polynomial when the one or more errors are found based on the first error evaluator polynomial in the input Reed-Solomon codeword, and
• wherein the error location polynomial coefficients in the memory are updated during each activation of the Reed-Solomon decoding when at least one error is identified in the Reed-Solomon codeword, and
• wherein the controller is configured to provide, via a direct memory access (DMA) controller, the decoded data to the host device.

A system for Reed-Solomon decoding, the system comprising:

• an interface coupled to a channel between a memory and a processing circuit;
• wherein the processing circuit is configured to implement a process for decoding a Reed-Solomon codeword starting with a partial input data of symbols of the Reed-Solomon codeword,
• wherein the processing circuit is configured to:
• obtain, via the channel, encoded data stored in the memory;
• and
• decode the encoded data using a Reed-Solomon decoder by detecting and correcting one or more errors in the encoded data to obtain decoded data, and
• wherein the detecting and correcting comprises:
• updating Reed-Solomon syndromes based on the partial input data of symbols of the Reed-Solomon codeword received via the Interface;
• updating error location polynomial coefficients based on the partial input data;
• maintaining the Reed-Solomon syndromes and the error location polynomial coefficients in a memory prior to starting activation of Reed-Solomon decoding;
• inputting the Reed-Solomon syndromes and the error location polynomial coefficients to a first activation of the Reed-Solomon decoding, the first activation including calculating an initial error evaluator polynomial as a first error evaluator polynomial, performing error detection on the encoded data based on the first error evaluator polynomial to determine presence and location of the one or more errors in an input Reed-Solomon codeword, and updating the error location polynomial when the one or more errors are found based on the first error evaluator polynomial in the input Reed-Solomon codeword, wherein the error location polynomial coefficients in the memory are updated during each activation of the Reed-Solomon decoding when at least one error is identified in the Reed-Solomon codeword, and
• providing, via a direct memory access (DMA) controller, the decoded data to a host device.