Multi-level gate driver applied to SiC MOSFET

A multi-level gate driver applied to a SiC metal-oxide-semiconductor field-effect transistor (MOSFET), comprising:

• a SiC MOSFET information detection circuit, a signal level shifting circuit, and a segmented driving circuit, wherein the SiC MOSFET information detection circuit comprises a SiC MOSFET drain-source voltage detection circuit and a SiC MOSFET drain-source current detection circuit, the SiC MOSFET drain-source voltage detection circuit and the SiC MOSFET drain-source current detection circuit are respectively configured to perform sampling on information about a drain-source voltage of the SiC MOSFET and a drain-source current of the SiC MOSFET to obtain enable signals, the signal level shifting circuit is configured to transfer the enable signal for segmented driving to a level matching the segmented driving circuit and transmit the enable signal for segmented driving to the segmented driving circuit, and the segmented driving circuit comprises a turn-on segmented driving circuit and a turn-off segmented driving circuit and the segmented driving circuit is configured to drive the SiC MOSFET according to the enable signals for segmented driving, wherein
• the SiC MOSFET drain-source voltage detection circuit comprises a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate, a fifth NOT gate, a sixth NOT gate, a seventh NOT gate, an eighth NOT gate, a ninth NOT gate, a tenth NOT gate, an eleventh NOT gate, a twelfth NOT gate, a first AND gate, a second AND gate, a first Zener diode, a first Schottky diode, a second Zener diode, a second Schottky diode, a first latch, a second latch, a N-metal-oxide-semiconductor (NMOS) transistor, a P-metal-oxide-semiconductor (PMOS) transistor, a first delay circuit, a second delay circuit, a first rising edge detection circuit, a second rising edge detection circuit, a third rising edge detection circuit, a fourth rising edge detection circuit, a fifth rising edge detection circuit, a sixth rising edge detection circuit, a seventh rising edge detection circuit, an eighth rising edge detection circuit, a first falling edge detection circuit, a second falling edge detection circuit, and a level shifter, wherein an input end of the first NOT gate, an input end of the second NOT gate, an input end of the third NOT gate, and an input end of the fourth NOT gate are connected to the SiC MOSFET drain-source voltage detection circuit and a negative electrode of the first Zener diode, and a positive electrode of the first Zener diode is grounded;
• an output end of the first NOT gate is connected to an input end of the first rising edge detection circuit, and the first rising edge detection circuit outputs a first turn-on control signal;
• an output end of the second NOT gate is connected to an input end of the second rising edge detection circuit, and the second rising edge detection circuit outputs a second turn-on control signal;
• an output end of the third NOT gate is connected to an input end of the third rising edge detection circuit, and an output end of the fourth NOT gate is connected to an input end of the fifth NOT gate;
• an output end of the fifth NOT gate is connected to an input end of the fourth rising edge detection circuit, an output end of the fourth rising edge detection circuit is connected to an input end of the first delay circuit, an output end of the first delay circuit is connected to a first input end of the first AND gate, a second input end of the first AND gate is connected to an output end of the fifth rising edge detection circuit, an input end of the fifth rising edge detection circuit is connected to an output end of the sixth NOT gate, an input end of the sixth NOT gate is connected to an output end of the level shifter, and an input end of the level shifter is configured to receive a first driving input signal;
• an output end of the first AND gate is connected to an R input end of the first latch, an S input end of the first latch is connected to the output end of the first delay circuit, an output end of the first latch is connected to an input end of the seventh NOT gate, an output end of the seventh NOT gate is connected to a gate of the PMOS transistor, a source of the PMOS transistor is grounded, a drain of the PMOS transistor is connected to an anode of the first Schottky diode, and a cathode of the first Schottky diode is connected to the SiC MOSFET drain-source voltage detection circuit;
• an input end of the eighth NOT gate, an input end of the ninth NOT gate, an input end of the tenth NOT gate, and an input end of the twelfth NOT gate and an anode of the second Zener diode are connected to the SiC MOSFET drain-source voltage detection circuit, and a cathode of the second Zener diode is connected to a power supply;
• an output end of the eighth NOT gate is connected to the first falling edge detection circuit, and the first falling edge detection circuit outputs a first turn-off control signal;
• an output end of the ninth NOT gate is connected to the second falling edge detection circuit, and an output end of the second falling edge detection circuit outputs a second turn-off control signal;
• an output end of the tenth NOT gate is connected to an input end of the eleventh NOT gate, and an output end of the eleventh NOT gate is connected to the sixth rising edge detection circuit;
• an output end of the twelfth NOT gate is connected to an input end of the seventh rising edge detection circuit, an output end of the seventh rising edge detection circuit is connected to the second delay circuit, an output end of the second delay circuit is connected to a first input end of the second AND gate, a second input end of the second AND gate is connected to an output end of the eighth rising edge detection circuit, and an input end of the eighth rising edge detection circuit is configured to receive a second driving input signal;
• and an output end of the second AND gate is connected to an R input end of the second latch, an S input end of the second latch is connected to an output end of the sixth rising edge detection circuit, an output end of the second latch is connected to a gate of the NMOS transistor, a source of the NMOS transistor is grounded, a drain of the NMOS transistor is connected to a cathode of the second Schottky diode, and an anode of the second Schottky diode is connected to the SiC MOSFET drain-source voltage detection circuit;
• the SiC MOSFET drain-source current detection circuit comprises a thirteen NOT gate, a fourteenth NOT gate, a fifteenth NOT gate, a sixteenth NOT gate, a seventeenth NOT gate, a Schmitt trigger, a third Zener diode, a fourth Zener diode, a third latch, a third AND gate, a ninth rising edge detection circuit, a tenth rising edge detection circuit, an eleventh rising edge detection circuit, and a divide-by-two circuit, wherein an input end of the thirteen NOT gate, an input end of the sixteenth NOT gate, an anode of the third Zener diode, and a cathode of the fourth Zener diode are connected to the SiC MOSFET drain-source current detection circuit, a cathode of the third Zener diode is connected to the power supply, and an anode of the fourth Zener diode is grounded;
• an output end of the thirteen NOT gate is connected to an input end of the fourteenth NOT gate, an output end of the fourteenth NOT gate is connected to a clock signal input end of the divide-by-two circuit, and a reset signal end of the divide-by-two circuit is connected to an output end of the third latch;
• an S input end of the third latch is connected to an output end of the ninth rising edge detection circuit, and an R input end of the third latch is connected to an output end of the tenth rising edge detection circuit;
• an input end of the ninth rising edge detection circuit is configured to receive a third driving input signal, and an input end of the tenth rising edge detection circuit is connected to an output end of the third AND gate;
• an output end of the divide-by-two circuit is connected to an input end of the eleventh rising edge detection circuit, an output end of the eleventh rising edge detection circuit is connected to an input end of the fifteenth NOT gate, an output end of the fifteenth NOT gate is connected to a first input end of the third AND gate, a second input end of the third AND gate is connected to the output end of the third latch, and the third AND gate outputs a third turn-on control signal;
• and an output end of the sixteenth NOT gate is connected to an input end of the Schmitt trigger, an output end of the Schmitt trigger is connected to an input end of the seventeenth NOT gate, and an output end of the seventeenth NOT gate outputs a third turn-off control signal;
• the first turn-on control signal, the second turn-on control signal, the third turn-on control signal, the first turn-off control signal, the second turn-off control signal, the third turn-off control signal, and an externally inputted control signal form the enable signals for segmented driving, a signal level shifting circuit comprises an upward shifting and a downward shifting;
• and a first high-level turn-on control signal, a second high-level turn-on control signal, a third high-level turn-on control signal, a high-level externally inputted control signal, a first low-level turn-off control signal, a second low-level turn-off control signal, a third low-level turn-off control signal, and a low-level externally inputted control signal are obtained after the enable signals for segmented driving pass through the signal level shifting circuit;
• the turn-on segmented driving circuit comprises an eighteenth NOT gate, a nineteenth NOT gate, a twentieth NOT gate, a twenty-first NOT gate, a twenty-second NOT gate, a twenty-third NOT gate, a twenty-fourth NOT gate, a twenty-fifth NOT gate, a twenty-sixth NOT gate, a first OR-NOT gate, a fourth AND gate, a first AND-NOT gate, a second AND-NOT gate, a fourth latch, a fifth latch, a first p-type lateral diffused metal oxide semiconductor (PLDMOS) transistor, a second PLDMOS transistor, a third PLDMOS transistor, and a twelfth rising edge detection circuit, wherein an input end of the nineteenth NOT gate is configured to receive the high-level externally inputted control signal, and an output end of the nineteenth NOT gate is connected to a first input end of the first OR-NOT gate and an R input end of the fifth latch;
• a second input end of the first OR-NOT gate is connected to an output end of the eighteenth NOT gate, and an output end of the first OR-NOT gate is connected to an R input end of the fourth latch;
• an input end of the eighteenth NOT gate is configured to receive the first high-level turn-on control signal;
• an S input end of the fourth latch is connected to an output end of the twelfth rising edge detection circuit, and an input end of the twelfth rising edge detection circuit is configured to receive the third high-level turn-on control signal;
• an input end of the twenty-second NOT gate is connected to an output end of the fourth latch, an output end of the twenty-second NOT gate is connected to a first input end of the first AND-NOT gate, a second input end of the first AND-NOT gate is connected to an output end of the twenty-first NOT gate, an output end of the first AND-NOT gate is connected to an input end of the twenty-third NOT gate, an output end of the twenty-third NOT gate is connected to an input end of the twenty-fourth NOT gate, an output end of the twenty-fourth NOT gate is connected to a gate of the first PLDMOS transistor, and a source of the first PLDMOS transistor is connected to the power supply;
• an S input end of the fifth latch is configured to receive the second high-level turn-on control signal, an output end of the fifth latch is connected to a first input end of the second AND-NOT gate, a second input end of the second AND-NOT gate is connected to an output end of the fourth AND gate, an output end of the second AND-NOT gate is connected to an input end of the twenty-fifth NOT gate, an output end of the twenty-fifth NOT gate is connected to an input end of the twenty-sixth NOT gate, an output end of the twenty-sixth NOT gate is connected to a gate of the third PLDMOS transistor, and a source of the third PLDMOS transistor is connected to the power supply;
• a first input end of the fourth AND gate is configured to receive the high-level externally inputted control signal, a second input end of the fourth AND gate is configured to receive a SiC MOSFET turn-on stage deadband signal, and the output end of the fourth AND gate is connected to an input end of the twentieth NOT gate;
• and an output end of the twentieth NOT gate is connected to an input end of the twenty-first NOT gate and a gate of the second PLDMOS transistor, and a source of the second PLDMOS transistor is connected to the power supply;
• and
• the turn-off segmented driving circuit comprises a twenty-seventh NOT gate, a twenty-eighth NOT gate, a twenty-ninth NOT gate, a thirtieth NOT gate, a thirty-first NOT gate, a thirty-second NOT gate, a thirty-third NOT gate, a thirty-fourth NOT gate, a second OR-NOT gate, a third OR-NOT gate, a third AND-NOT gate, a fifth AND gate, a sixth AND gate, a seventh AND gate, a sixth latch, a seventh latch, an eighth latch, a first n-type laterally diffused metal-oxide-semiconductor (NLDMOS) transistor, a second NLDMOS transistor, a third NLDMOS transistor, a third delay circuit, a third falling edge detection circuit, a fourth falling edge detection circuit, and a thirteenth rising edge detection circuit, wherein a first input end of the second OR-NOT gate is configured to receive the second low-level turn-off control signal, a second input end of the second OR-NOT gate is configured to receive the low-level externally inputted control signal, an output end of the second OR-NOT gate is connected to an input end of the twenty-seventh NOT gate, and an output end of the twenty-seventh NOT gate is connected to an R input end of the sixth latch;
• an S input end of the sixth latch is configured to receive the first low-level turn-off control signal, an output end of the sixth latch is connected to an input end of the third delay circuit, an input end of the third falling edge detection circuit, and an input end of the thirtieth NOT gate, an output end of the thirtieth NOT gate is connected to a first input end of the sixth AND gate, a second input end of the sixth AND gate is connected to an output end of the third OR-NOT gate, an output end of the sixth AND gate is connected to an input end of the thirty-first NOT gate, an output end of the thirty-first NOT gate is connected to an input end of the thirty-second NOT gate, an output end of the thirty-second NOT gate is connected to a gate of the first NLDMOS transistor, and a source of the first NLDMOS transistor is grounded;
• an input end of the thirteenth rising edge detection circuit is connected to an output end of the third delay circuit, an output end of the thirteenth rising edge detection circuit is connected to an input end of the twenty-eighth NOT gate, an output end of the twenty-eighth NOT gate is connected to a first input end of the fifth AND gate, a second input end of the fifth AND gate is connected to an output end of the third AND-NOT gate, a first input end of the third AND-NOT gate is connected to an output end of the seventh latch, and a second input end of the third AND-NOT gate is connected to an output end of the fourth falling edge detection circuit;
• an input end of the fourth falling edge detection circuit is configured to receive the third low-level turn-off control signal;
• an S input end of the seventh latch is connected to an output end of the third falling edge detection circuit, and an R input end of the seventh latch is configured to receive the low-level externally inputted control signal;
• an output end of the fifth AND gate is connected to an S input end of the eighth latch, an R input end of the eighth latch is connected to an output end of the twenty-ninth NOT gate, and an input end of the twenty-ninth NOT gate is configured to receive a low-level externally outputted control signal;
• a first input end of the seventh AND gate is connected to an output end of the eighth latch, a second input end of the seventh AND gate is connected to the output end of the third OR-NOT gate, an output end of the seventh AND gate is connected to an input end of the thirty-third NOT gate, an output end of the thirty-third NOT gate is connected to an input end of the thirty-fourth NOT gate, an output end of the thirty-fourth NOT gate is connected to a gate of the third NLDMOS transistor, and a source of the third NLDMOS transistor is grounded;
• a gate of the second NLDMOS transistor is connected to the output end of the third OR-NOT gate, and a source of the second NLDMOS transistor is grounded;
• and a drain of the first PLDMOS transistor, a drain of the second PLDMOS transistor, a drain of the third PLDMOS transistor, a drain of the first NLDMOS transistor, a drain of the second NLDMOS transistor, and a drain of the third NLDMOS transistor are connected as an output end of a segmented driving circuit.