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US 12,197,970 B2Granted
Processing system with interspersed processors DMA-FIFO
AssigneeHyperX Logic, Inc.
InventorsCarl S. Dobbs, Michael R. Trocino, Keith M. Bindloss
Life of this patent
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Abstract
Embodiments of a multi-processor array are disclosed that may include a plurality of processors, local memories, configurable communication elements, and direct memory access (DMA) engines, and a DMA controller. Each processor may be coupled to one of the local memories, and the plurality of processors, local memories, and configurable communication elements may be coupled together in an interspersed arrangement. The DMA controller may be configured to control the operation of the plurality of DMA engines.
Claims17
An apparatus, comprising:
- a plurality of processors;
- a plurality of memory circuits coupled to the plurality of processors in an interspersed fashion;
- a plurality of configurable communication elements that includes a given configurable communication element that includes a plurality of communication ports and a routing engine;
- a plurality of direct memory access (DMA) engines including a given DMA engine configured to transfer data between a particular memory circuit of the plurality of memory circuits and a particular configurable communication element of the plurality of configurable communication elements, wherein to transfer the data, the given DMA engine is configured to:
- receive an input data stream;
- determine a particular write address to store a portion of the input data stream in a buffer located in a portion of the particular memory circuit;
- in response to a determination that the particular write address exceeds an end address of the buffer, change a value of the particular write address to a start address of the buffer to generate a modified write address;
- store the portion of the input data stream using the modified write address;
- increment a previous read address to generate a current read address;
- in response to a determination that the current read address is the same as the modified write address, generate a read stall signal;
- send the read stall signal to a destination of an output data stream being read from the given DMA engine to prevent data duplication, wherein the read stall signal causes DMA engines between the given DMA engine and the destination to stall read and write operations;
- and
- after sending the read stall signal, send a de-assertion signal to the destination of the output data stream to resume writing the output data stream after the portion of the input data stream is stored in the buffer.
10 more elements
A method, comprising:
- executing at least one program on a plurality of processors in a multiprocessor system;
- receiving, by a first direct memory access (DMA) engine of a plurality of DMA engines, a first input data stream;
- determining a first address to store a portion of the first input data stream in a buffer located in a portion of a particular memory circuit of a plurality of memory circuits coupled to the plurality of processors in an interspersed fashion;
- in response to determining that the first address exceeds an end address of the buffer, changing a value of the first address to a start address of the buffer to generate a modified first address;
- storing the portion of the first input data stream using the modified first address;
- incrementing a previous read address to generate a current read address;
- in response to determining that the current read address is the same as the modified write address, generating a read stall signal;
- sending the read stall signal to a destination of an output data stream being read from the first DMA engine to prevent data duplication, wherein the read stall signal causes DMA engines between the given DMA engine and the destination to stall read and write operations;
- and
- after sending the read stall signal, sending a de-assertion signal to the destination of the output data stream to resume writing the output data stream after the portion of the input data stream is stored in the buffer.
7 more elements
A system, comprising:
- a plurality of processors;
- a plurality of memory circuits including a given memory circuit coupled to a subset of the plurality of processors;
- a plurality of direct memory access (DMA) engines including a first DMA engine configured to:
- receive a first input data stream with a first data rate;
- determine a first address to store a portion of the first input data stream in a buffer located in a portion of a particular memory circuit;
- in response to a determination that the first address exceeds an end address of the buffer, change a value of the first address to a start address of the buffer to generate a modified first address;
- and
- store the portion of the first input data stream using the modified first address;
- increment a previous read address to generate a current read address;
- in response to a determination that the current read address is the same as the modified write address, generate a read stall signal;
- send the read stall signal to a destination of an output data stream being read from the first DMA engine to prevent data duplication, wherein the read stall signal causes DMA engines between the given DMA engine and the destination to stall read and write operations;
- and
- after sending the read stall signal, send a de-assertion signal to the destination of the output data stream to resume writing the output data stream after the portion of the input data stream is stored in the buffer.
10 more elements
Dependencies are inferred from the claim text.