Semiconductor memory device

A semiconductor memory device comprising:

• a storage memory comprising a nonvolatile memory and a nonvolatile memory controller configured to control the nonvolatile memory;
• a main memory comprising a volatile memory and a volatile memory controller configured to control the volatile memory;
• an access controller communicatively coupled to the storage memory and the main memory and configured to perform data communication with an external device based on a first protocol, perform data communication with the storage memory based on a second protocol, perform data communication with the main memory based on a third protocol, and control access from the external device to the storage memory and the main memory;
• a first crossbar configured to enable data communication by connecting the access controller and the storage memory;
• a second crossbar configured to enable data communication by connecting the access controller and the main memory;
• and
• a third crossbar configured to connect the first crossbar and the second crossbar.

An access controller comprising:

• a first interface configured to perform data communication based on a first protocol with a first external device;
• a second interface configured to perform data communication based on a second protocol with a second external device comprising a nonvolatile memory;
• a third interface configured to perform data communication based on a third protocol with a third external device comprising a volatile memory;
• a controller communicatively coupled to the second external device and configured to control an access to the nonvolatile memory;
• a link communicatively coupled to the controller, the first interface, the second interface, and the third interface and configured to process a first message received through the first interface, generate a second message based on the second protocol and transmit the second message to the second external device through the second interface, generate a third message based on the third protocol and transmit the third message to the third external device through the third interface, or transmit the processed first message to the controller;
• a fourth interface based on the second protocol, wherein the controller is configured to generate a fourth message based on the second protocol based on the first message and transmit the fourth message to the second external device through the fourth interface;
• and
• wherein the first interface is a peripheral component interconnection express (PCIe) interface, the second interface is a compute express link.io (CXL.io) interface, and the third interface is a CXL.mem interface.