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US 12,197,343 B2Granted
Streaming engine with multi dimensional circular addressing selectable at each dimension
AssigneeTexas Instruments Incorporated
InventorJoseph Zbiciak
Life of this patent
Estimating the term…
Abstract
A streaming engine employed in a digital data processor may specify a fixed read-only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template register independently specifies a linear address or a circular address mode for each of the nested loops.
Claims20
A device comprising:
- a first memory that stores a set of instructions that, when executed by a processor device, cause the processor device to:
- store a set of values in a register that includes:
- a first addressing mode value for a first loop that specifies whether to loop back to a first end of a first memory region when a second end of the first memory region is reached, wherein, when the first addressing mode value specifies to loop back to the first end of the first memory region, the set of values further specifies a size of the first memory region;
- and
- a second addressing mode value for a second loop that specifies whether to loop back to a first end of a second memory region when a second end of the second memory region is reached, wherein, when the second addressing mode value specifies to loop back to the first end of the second memory region, the set of values further specifies a size of the second memory region;
- and
- retrieve a set of data from a second memory based on the set of values by traversing the first memory region and the second memory region.
4 more elements
A device comprising:
- a first memory configured to store a set of data;
- a processor that includes a register configured to store a set of values that includes:
- a first addressing mode value for a first loop that specifies whether to loop back to a first end of a first memory region when a second end of the first memory region is reached, wherein, when the first addressing mode value specifies to loop back to the first end of the first memory region, the set of values further specifies a size of the first memory region;
- and
- a second addressing mode value for a second loop that specifies whether to loop back to a first end of a second memory region when a second end of the second memory region is reached, wherein, when the second addressing mode value specifies to loop back to the first end of the second memory region, the set of values further specifies a size of the second memory region;
- a memory control circuit coupled between the processor and the first memory;
- and
- a second memory configured to store a set of instructions, that when executed by the processor, cause the processor to cause the memory control circuit to provide the set of data from the first memory to the processor based on the set of values by traversing the first memory region and the second memory region.
5 more elements
A method comprising:
- storing a set of values in a register of a processor, wherein the set of values includes:
- a first addressing mode value for a first loop that specifies whether to loop back to a first end of a first memory region when a second end of the first memory region is reached, wherein, when the first addressing mode value specifies to loop back to the first end of the first memory region, the set of values further specifies a size of the first memory region;
- and
- a second addressing mode value for a second loop that specifies whether to loop back to a first end of a second memory region when a second end of the second memory region is reached, wherein, when the second addressing mode value specifies to loop back to the first end of the second memory region, the set of values further specifies a size of the second memory region;
- and
- in response to an instruction:
- providing the set of values from the processor to a memory control circuit;
- and
- retrieving, using the memory control circuit, a set of data from a memory based on the set of values by traversing the first memory region and the second memory region.
6 more elements
Dependencies are inferred from the claim text.