Method for reducing line-end space in integrated circuit patterning
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJing-Huei Huang, Ya-Wen Chiu, Lun-Kuang Tan
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJing-Huei Huang, Ya-Wen Chiu, Lun-Kuang Tan
Estimating the term…
A method includes forming a resist pattern over a structure, the resist pattern having a trench surrounded by first resist walls extending lengthwise along a first direction and second resist walls extending lengthwise along a second direction perpendicular to the first direction. The method includes loading the structure and the resist pattern into an ion implanter so that a top surface of the resist pattern faces an ion travel direction of the ion implanter. The method includes tilting the structure and the resist pattern so that the ion travel direction forms a tilt angle with respect to an axis perpendicular to the top surface of the resist pattern. The method includes first rotating the structure and the resist pattern around the axis to a first position. The method includes first implanting ions into the resist pattern with the structure and the resist pattern at the first position.
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Dependencies are inferred from the claim text.