System for scan mode exit and methods for scan mode exit
AssigneeNXP B.V.
InventorsTarun Kumar Goyal, Nikila Krishnamoorthy
Life of this patent
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Abstract
Resetting an integrated circuit (IC) by reset circuit of the IC comprises receiving a clock signal and a data signal. A sequence of bits of the data signal is stored in a memory based on the clock signal. A test mode signal is received and the sequence of bits is decoded in response to receiving the test mode signal. One of adjusting a counter value of a counter of the reset circuitry and outputting a reset signal corresponding to the counter value is performed based on the decoded sequence of bits.
Claims18
A method for operating a reset circuit of an integrated circuit (IC), the method comprising:
- receiving, by the IC, a clock signal and a data signal from automatic test equipment;
- storing a sequence of bits of the data signal in a memory based on the clock signal;
- receiving, by the IC, a test mode signal;
- decoding the sequence of bits in response to receiving the test mode signal;
- based on the decoded sequence of bits indicating a counter adjust value, adjusting a counter value of a counter;
- based on the decoded sequence of bits indicating a reset value, outputting a reset signal to reset at least a portion of a plurality of portions of a functional circuit of the IC, wherein the counter value uniquely identifies which portion of the plurality of portions of the functional circuit is to be reset
- wherein the counter value of the counter of the reset circuitry is incremented when a value of the decoded sequence of bits is equal to the counter adjust value and the reset signal is output when the value of the decoded sequence of bits is equal to the reset value;
- and wherein the portion is indicated by the counter value when the value of the decoded sequence of bits is equal to the reset value.
An integrated circuit (IC) comprising:
- a functional circuit;
- a reset circuit arranged to receive a clock signal and a data signal from automatic test equipment;
- store a sequence of bits of the data signal in a memory based on the clock signal;
- receive a test mode signal;
- and decode the sequence of bits in response to receiving the test mode signal;
- a counter arranged to based on the decoded sequence of bits indicating a counter adjust value, adjust a counter value;
- and
- the reset circuit further arranged to based on the decoded sequence of bits indicating a reset value, output a reset signal to the functional circuit to reset at least a portion of the functional circuit of the IC, wherein the counter value uniquely identifies which portion of the plurality of portions of the functional circuit is to be reset, wherein the counter value of the counter of the reset circuitry is incremented when a value of the decoded sequence of bits is equal to the counter adjust value and the reset signal is output when the value of the decoded sequence of bits is equal to the reset value;
- and wherein the portion is indicated by the counter value when the value of the decoded sequence of bits is equal to the reset value.
Dependencies are inferred from the claim text.