# US 12,193,345 B2 · Method for forming resistive random access memory structure

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- Number: US 12,193,345 B2
- Document ID: US12193345B2
- Status: Granted
- Kind: B2
- Application number: 18/503,140
- Filed: 2023-11-06
- Published: 2024-02-29
- Granted: 2025-01-07
- Earliest claimed: 2020-12-30
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Wen-Jen Wang; Chun-Hung Cheng; Chuan-Fu Wang
- Web page: https://patentgrep.com/patent/US12193345B2

## CPC

- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10B 63/00: Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10N 70/023: {by chemical vapor deposition, e.g. MOCVD, ALD}
- H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/841: {Electrodes}
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A resistive random access memory (RRAM) structure includes a RRAM cell, spacers and a dielectric layer. The RRAM cell is disposed on a substrate. The spacers are disposed beside the RRAM cell, wherein widths of top surfaces of the spacers are larger than or equal to widths of bottom surfaces of the spacers. The dielectric layer blanketly covers the substrate and sandwiches the RRAM cell, wherein the spacers are located in the dielectric layer. A method for forming the resistive random access memory (RRAM) structure is also provided.

## Claims

### Claim 1

A resistive random access memory (RRAM) forming method, comprising:
forming a RRAM cell on a substrate;
depositing a dielectric layer blanketly covering the substrate beside the RRAM cell;
etching the dielectric layer to form recesses in the dielectric layer beside the RRAM cell; and
spacers filling into the recesses, wherein the spacers comprise at least one of silicon nitride (SiN), silicon carbide (SiC), nitrogen containing silicon carbide (SiCN), carbon containing silicon oxynitride (SiCNO).

### Claim 2 (depends on 1)

The resistive random access memory (RRAM) forming method according to claim 1, further comprising:
forming an oxide layer conformally covering the RRAM cell before the dielectric layer is deposited.

### Claim 3 (depends on 1)

The resistive random access memory (RRAM) forming method according to claim 1, wherein steps of spacers filling into the recesses comprise:
forming a spacer material in the recesses and on the dielectric layer; and
removing a part of the spacer material exceeding from the recesses.

### Claim 4 (depends on 3)

The resistive random access memory (RRAM) forming method according to claim 3, wherein the spacer material is formed by an atomic layer deposition (ALD) process.

### Claim 5 (depends on 1)

The resistive random access memory (RRAM) forming method according to claim 1, wherein the spacers have oblique sidewalls broaden from bottom to top.

### Claim 6 (depends on 5)

The resistive random access memory (RRAM) forming method according to claim 5, wherein the spacers have trapezoidal shape cross-sectional profiles.

### Claim 7 (depends on 1)

The resistive random access memory (RRAM) forming method according to claim 1,
wherein the substrate comprises an ultra-low k dielectric layer, a nitrogen containing silicon carbide (SiCN) layer and a silicon oxide layer stacked from bottom to top.

### Claim 8 (depends on 7)

The resistive random access memory (RRAM) forming method according to claim 7, further comprising forming a via disposed in the silicon oxide layer and the nitrogen containing silicon carbide (SiCN) layer, and wherein the via directly contacting the RRAM cell, and a metal interconnect disposed in the ultra-low k dielectric layer and directly contacting the via.

### Claim 9 (depends on 1)

The resistive random access memory (RRAM) forming method according to claim 1, wherein the spacers directly contact the substrate.

### Claim 10 (depends on 9)

The resistive random access memory (RRAM) forming method according to claim 9, wherein a bottom part of each of the spacers extends to the substrate.

### Claim 11 (depends on 1)

The resistive random access memory (RRAM) forming method according to claim 1, wherein the spacers are only in top parts of the dielectric layer.

### Claim 12 (depends on 1)

The resistive random access memory (RRAM) forming method according to claim 1, wherein the RRAM cell comprises a bottom electrode, a resistive material layer and a top electrode stacked from bottom to top.

### Claim 13 (depends on 12)

The resistive random access memory (RRAM) forming method according to claim 12, further comprising forming a top via and a bottom via, and the top via, the bottom via and the RRAM cell disposed in the dielectric layer, wherein the top via contacts the top electrode and the bottom via contacts the bottom electrode.

### Claim 14 (depends on 1)

The resistive random access memory (RRAM) forming method according to claim 1, wherein a part of the dielectric layer is between the spacers and the RRAM cell.