# US 12,193,344 B2 · Method for manufacturing resistive random access memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,193,344 B2 - Document ID: US12193344B2 - Status: Granted - Kind: B2 - Application number: 18/452,853 - Filed: 2023-08-21 - Published: 2023-12-07 - Granted: 2025-01-07 - Earliest claimed: 2019-11-22 - Assignees: Winbond Electronics Corp. - Applicants: Winbond Electronics Corp. - Inventors: Cheng-Hong Wei; Chien-Hsiang Yu; Hung-Sheng Chen - Web page: https://patentgrep.com/patent/US12193344B2 ## CPC - H10N 70/24: {based on migration or redistribution of ionic species, e.g. anions, vacancies} - H10N 70/841: {Electrodes} - H10B 63/00: Resistance change memory devices, e.g. resistive RAM [ReRAM] devices - H10N 70/011: {Manufacture or treatment of multistable switching devices} - H10N 70/021: {Formation of switching materials, e.g. deposition of layers} - H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography} - H10N 70/245: {the species being metal cations, e.g. programmable metallization cells} - H10N 70/823: {adapted for essentially horizontal current flow, e.g. bridge type devices} - H10N 70/8833: {Binary metal oxides, e.g. TaOx} - H10N 70/8836: {Complex metal oxides, e.g. perovskites, spinels} - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A RRAM and its manufacturing method are provided. The RRAM includes a first dielectric layer formed on a substrate, and two memory cells. The two memory cells include two bottom electrode structures separated from each other. Each bottom electrode structure fills one of two trenches in the first dielectric layer. The two memory cells also include a resistance switching layer and a top electrode structure. The resistance switching layer is conformally formed on the surface of an opening in the first dielectric layer, and the opening is between the two trenches. The top electrode structure is on the resistance switching layer and fills the opening. A top surface of the first dielectric layer, top surfaces of the bottom electrode structures, a top surface of the resistance switching layer, and a top surface of the top electrode structure are coplanar. ## Claims ### Claim 1 A method for manufacturing a RRAM, comprising: forming a first dielectric layer on a substrate; and forming two memory cells, comprising: forming two trenches in the first dielectric layer; forming two bottom electrode structures separated from each other, wherein each of the bottom electrode structures fills one of the trenches located in the first dielectric layer; forming an opening between the two trenches; conformally forming a resistance switching layer on a surface of the opening; forming a top electrode structure on the resistance switching layer and filling the opening; and performing a planarization process to make a top surface of the first dielectric layer, top surfaces of the bottom electrode structures, a top surface of the resistance switching layer, and a top surface of the top electrode structure be substantially coplanar. ### Claim 2 (depends on 1) The method for manufacturing the RRAM as claimed in claim 1, wherein the trench has a first depth D1, the opening has a second depth D2, and the second depth D2 is greater than the first depth D1. ### Claim 3 (depends on 2) The method for manufacturing the RRAM as claimed in claim 2, wherein a ratio D2/D1 of the second depth D2 to the first depth D1 is 1.1-2.0. ### Claim 4 (depends on 1) The method for manufacturing the RRAM as claimed in claim 1, wherein the trench has a first width W1 and a first depth D1, and a ratio D1/W1 of the first depth D1 to the first width W1 is 1-10. ### Claim 5 (depends on 1) The method for manufacturing the RRAM as claimed in claim 1, wherein a thickness of the resistance switching layer is 1-100 nm. ### Claim 6 (depends on 1) The method for manufacturing the RRAM as claimed in claim 1, wherein the resistance switching layer has a U-shaped cross-sectional profile, and the U-shaped cross-sectional profile comprises two vertical portions and a horizontal portion connected to each other. ### Claim 7 (depends on 1) The method for manufacturing the RRAM as claimed in claim 1, wherein a bottom surface of each of the bottom electrode structures is higher than a bottom surface of the top electrode structure. ### Claim 8 (depends on 1) The method for manufacturing the RRAM as claimed in claim 1, wherein a bottom surface of each of the bottom electrode structures is level with a bottom surface of the top electrode structure. ### Claim 9 (depends on 1) The method for manufacturing the RRAM as claimed in claim 1, further comprising: forming two bottom electrode contact structures in the first dielectric layer; after forming the bottom electrode contact structures, forming the trenches directly on the bottom electrode contact structures, wherein each of the bottom electrode contact structures is electrically connected to one of the bottom electrode structures; forming a second dielectric layer covering the bottom electrode structures, the resistance switching layer, and the top electrode structure; and forming a top electrode contact structure in the second dielectric layer and on the top electrode structure, wherein the top electrode contact structure is electrically connected to the top electrode structure, and wherein an orthographic projection of the top electrode contact structure on the substrate and an orthographic projection of each of the bottom electrode contact structures on the substrate do not overlap. ### Claim 10 (depends on 9) The method for manufacturing the RRAM as claimed in claim 9, further comprising: after performing a planarization process, forming a protective layer on the first dielectric layer; and forming a conductive line on the second dielectric layer and electrically connected to the top electrode contact structure. ### Claim 11 (depends on 10) The method for manufacturing the RRAM as claimed in claim 10, wherein the protective layer is a dual-layer structure. ### Claim 12 (depends on 11) The method for manufacturing the RRAM as claimed in claim 11, wherein the dual-layer structure is formed by a hydrogen barrier layer and a spacer layer formed on the hydrogen barrier layer. ### Claim 13 (depends on 10) The method for manufacturing the RRAM as claimed in claim 10, wherein the protective layer is a single layer structure. ### Claim 14 (depends on 13) The method for manufacturing the RRAM as claimed in claim 13, wherein the single layer structure is formed of silicon nitride. ### Claim 15 (depends on 1) The method for manufacturing the RRAM as claimed in claim 1, further comprising: after forming the resistance switching layer, conformally forming a function layer in the opening, wherein the function layer is an oxygen ion reservoir layer, a barrier layer, or a combination thereof. ### Claim 16 (depends on 15) The method for manufacturing the RRAM as claimed in claim 15, wherein the function layer is a dual-layer structure. ### Claim 17 (depends on 16) The method for manufacturing the RRAM as claimed in claim 16, wherein the dual-layer structure is formed by the oxygen ion reservoir layer and the barrier layer. ### Claim 18 (depends on 1) The method for manufacturing the RRAM as claimed in claim 1, further comprising: before forming the resistance switching layer, conformally forming a function layer in the opening, wherein the function layer is an oxygen ion reservoir layer, a barrier layer, or a combination thereof. ### Claim 19 (depends on 18) The method for manufacturing the RRAM as claimed in claim 18, wherein the function layer is a dual-layer structure. ### Claim 20 (depends on 19) The method for manufacturing the RRAM as claimed in claim 19, wherein the dual-layer structure is formed by the oxygen ion reservoir layer and the barrier layer.