# US 12,193,338 B2 · Reservoir computer with a series array of Josephson junctions

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- Number: US 12,193,338 B2
- Document ID: US12193338B2
- Status: Granted
- Kind: B2
- Application number: 17/094,694
- Filed: 2020-11-10
- Published: 2022-03-24
- Granted: 2025-01-07
- Earliest claimed: 2020-09-22
- Assignees: Rtx Bbn Technologies, Inc.
- Applicants: Raytheon Bbn Technologies Corp.
- Inventors: Graham Earle Rowlands; Thomas Akira Ohki; Guilhem Jean Antoine Ribeill; Minh-Hai Nguyen
- Web page: https://patentgrep.com/patent/US12193338B2

## CPC

- G06N 3/08: Learning methods
- H10N 60/0912: {of Josephson-effect devices}
- G06N 3/044: Recurrent networks, e.g. Hopfield networks
- G06N 3/063: using electronic means
- G06N 3/065: Analogue means
- G06N 3/09: Supervised learning
- G06N 10/00: Quantum computing, i.e. information processing based on quantum-mechanical phenomena
- G06N 10/40: Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
- G11C 11/44: using super-conductive elements, e.g. cryotron
- G11C 11/54: using elements simulating biological cells, e.g. neuron
- H10N 60/12: Josephson-effect devices
- H10N 60/128: {having three or more electrodes, e.g. transistor-like structures}
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A reservoir computer. In some embodiments, the reservoir computer includes a series array of Josephson junctions, a coupling impedance, and a readout circuit. In some embodiments, the series array of Josephson junctions includes a plurality of Josephson junctions, connected in series; the coupling impedance is connected in parallel with the series array of Josephson junctions; and the readout circuit is connected to at least three nodes of the series array of Josephson junctions.

## Claims

### Claim 1

A system, comprising:
a series array of Josephson junctions;
a coupling impedance; and
a readout circuit,
wherein:
the series array of Josephson junctions comprises a plurality of Josephson junctions, connected in series,
the coupling impedance is connected in parallel with the series array of Josephson junctions,
the readout circuit is connected to at least three nodes of the series array of Josephson junctions;
a first Josephson junction of the series array of Josephson junctions has a first critical current;
a second Josephson junction of the series array of Josephson junctions has a second critical current; and
the second critical current differs from the first critical current by approximately 2%.

### Claim 2 (depends on 1)

The system of claim 1, further comprising a current source connected in series with the parallel combination of the series array of Josephson junctions and the coupling impedance.

### Claim 3 (depends on 1)

The system of claim 1, wherein a first Josephson junction of the series array of Josephson junctions has a Stewart McCumber parameter within 50% of 1.0.

### Claim 4 (depends on 1)

The system of claim 1, further comprising an external shunt capacitor connected in parallel with a first Josephson junction of the series array of Josephson junctions.

### Claim 5 (depends on 4)

The system of claim 4, further comprising a first external shunt resistor connected in parallel with the first Josephson junction.

### Claim 6 (depends on 5)

The system of claim 5, wherein:
the coupling impedance comprises a resistor having a resistance within 30% of N times a resistance of the first external shunt resistor, and
N is the number of Josephson junctions in the series array of Josephson junctions.

### Claim 7 (depends on 1)

The system of claim 1, wherein the coupling impedance comprises an inductor.

### Claim 8 (depends on 7)

The system of claim 7, wherein:
the inductor has an inductance within 30% of 3N times a Josephson inductance of a Josephson junction of the series array of Josephson junctions, and
N is the number of Josephson junctions in the series array of Josephson junctions.

### Claim 9 (depends on 1)

The system of claim 1, wherein the series array of Josephson junctions comprises 3 Josephson junctions.

### Claim 10 (depends on 1)

The system of claim 1, wherein the series array of Josephson junctions comprises 5 Josephson junctions.

### Claim 11 (depends on 1)

The system of claim 1, wherein the readout circuit is connected to at most 15 nodes of the series array of Josephson junctions.

### Claim 12 (depends on 1)

The system of claim 1, further comprising a data transmission channel connected to the series array of Josephson junctions.