# US 12,193,337 B2 · Semiconductor device and method of fabricating the same

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- Number: US 12,193,337 B2
- Document ID: US12193337B2
- Status: Granted
- Kind: B2
- Application number: 16/991,055
- Filed: 2020-08-12
- Published: 2021-02-25
- Granted: 2025-01-07
- Earliest claimed: 2019-08-22
- Assignees: Winbond Electronics Corp.
- Applicants: Winbond Electronics Corp.
- Inventors: Wen-Chia Ou; Chih-Chao Huang; Min-Chih Wei; Yu-Ting Chen; Chi-Ching Liu
- Web page: https://patentgrep.com/patent/US12193337B2

## CPC

- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10N 50/80: Constructional details
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10N 50/01: Manufacture or treatment
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A method of fabricating a semiconductor device includes the following steps. A plurality of doped regions are formed in a substrate. A first dielectric layer is formed on the substrate. A plurality of first contacts and second contacts are formed in the first dielectric layer to be connected to the plurality of doped regions. A memory element is formed on the first dielectric layer. The memory element is electrically connected to the second contact. A second dielectric layer is formed on the first dielectric layer. The second dielectric layer surrounds the memory element. A conductive line is formed in the second dielectric layer. A top surface of the conductive line is at a same level as a top surface of the memory element, and the conductive line is electrically connected to the plurality of first contacts.

## Claims

### Claim 1

A semiconductor device, comprising:
a plurality of doped regions, located in a substrate;
a first dielectric layer, located on the substrate;
a plurality of first contacts and second contacts, located in the first dielectric layer and connected to the plurality of doped regions;
a second dielectric layer, located on the first dielectric layer;
a memory element, located in the second dielectric layer, the memory element being electrically connected to the second contact;
a conductive line, located in the second dielectric layer, the conductive line being electrically connected to the plurality of first contacts, a bottom surface of the conductive line being at a same level as a bottom surface of the memory element, and a top surface of the conductive line being at a same level as a top surface of the memory element;
an etch stop layer, located on the second dielectric layer;
a first inter-metal dielectric layer, located on the etch stop layer; and
a first dual damascene structure and a second dual damascene structure, located in the first inter-metal dielectric layer and the etch stop layer, the first dual damascene structure being connected to the conductive line and the second dual damascene structure being connected to the memory element, wherein a maximum height of the second dual damascene structure on the top surface of the memory element is greater than a maximum height of the first dual damascene structure, and
there is an interface between the first dual damascene structure and the conductive line,
wherein the conductive line is double-row comb-shaped on the substrate, and comprises:
a main line portion, extending along a first direction; and
a plurality of extending portions, extending along a second direction, arranged along the first direction, and penetrated through by the main line portion and connected to the main line portion and the plurality of first contacts,
wherein the memory element is blocky or island-shaped and arranged on two sides of the main line portion on the substrate.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein a top surface of the second dielectric layer is coplanar with the top surface of the conductive line and a top surface of a top cover layer of the memory element.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2, wherein the conductive line is in physical contact with the plurality of first contacts, and the memory element is in physical contact with the second contact.

### Claim 4 (depends on 2)

The semiconductor device according to claim 2, wherein the second dual damascene structure penetrates through the top cover layer of the memory element and is electrically connected to an electrode layer below the top cover layer.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a metal layer, arranged below the conductive line and the memory element and being in physical contact with the first contact; and
a plurality of vias, arranged between the metal layer and the conductive line and between the metal layer and the memory element.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein the conductive line comprises:
a main line portion, extending along a first direction; and
a plurality of extending portions, extending along a second direction, arranged along the first direction and connected to the main line portion and the plurality of first contacts.