# US 12,193,336 B2 · Structure and method for integrating MRAM and logic devices

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- Number: US 12,193,336 B2
- Document ID: US12193336B2
- Status: Granted
- Kind: B2
- Application number: 18/321,269
- Filed: 2023-05-22
- Published: 2023-09-21
- Granted: 2025-01-07
- Earliest claimed: 2020-11-25
- Assignees: Taiwan Semiconductoe Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Hsiang-Ku Shen; Dian-Hau Chen
- Web page: https://patentgrep.com/patent/US12193336B2

## CPC

- H10N 50/01: Manufacture or treatment
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10N 50/10: Magnetoresistive devices
- H10N 50/80: Constructional details
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A first metal layer extends across memory and logic device regions of a semiconductor structure. A dielectric barrier layer is disposed over the first metal layer. A first dielectric layer is disposed over the dielectric barrier layer in the memory device region and not in the logic device region. Multiple magnetic tunneling junction (MTJ) devices are disposed in the memory device region. A second dielectric layer is disposed in the memory device region and not in the logic device region. The second dielectric layer is disposed over the first dielectric layer and the MTJ devices. An extreme low-k dielectric layer is disposed over the dielectric barrier layer in the logic device region. A conductive feature in the logic device region penetrates the extreme low-k dielectric layer and the dielectric barrier layer to electrically connect to the first metal layer.

## Claims

### Claim 1

A structure having a memory device region and a logic device region, the structure comprising:
a first metal layer extending across an interface between the memory device region and the logic device region;
a dielectric barrier layer over the first metal layer in both the memory device region and the logic device region;
a first dielectric layer over the dielectric barrier layer in the memory device region;
multiple magnetic tunneling junction (MTJ) devices in the memory device region, wherein the MTJ devices are disposed over the first metal layer, the dielectric barrier layer, and the first dielectric layer;
a second dielectric layer in the memory device region, wherein the second dielectric layer is disposed over the first dielectric layer and the MTJ devices;
an extreme low-k dielectric layer over and in physical contact with the dielectric barrier layer in the logic device region and in physical contact with a sidewall of the first and second dielectric layers, wherein a portion of the extreme low-k dielectric layer is directly over the second dielectric layer in the memory device region; and
a conductive feature in the logic device region, penetrating the extreme low-k dielectric layer and the dielectric barrier layer, and electrically connecting to the first metal layer.

### Claim 2 (depends on 1)

The structure of claim 1, wherein the second dielectric layer includes silicon carbonitride and the first dielectric layer includes silicon oxide.

### Claim 3 (depends on 1)

The structure of claim 1, wherein the extreme low-k dielectric layer includes silicon, oxygen, carbon, hydrogen, and nitrogen.

### Claim 4 (depends on 1)

The structure of claim 1, wherein each of the MTJ devices includes:
a bottom electrode via that penetrates the first dielectric layer and the dielectric barrier layer and electrically connects to the first metal layer,
a bottom electrode over the bottom electrode via and the first dielectric layer,
an MTJ stack over the bottom electrode,
a top electrode over the MTJ stack, and
a dielectric spacer over sidewalls of the MTJ stack and the first dielectric layer.

### Claim 5 (depends on 4)

The structure of claim 4, further comprising a layer comprising aluminum oxide and disposed between the dielectric spacer and the second dielectric layer.

### Claim 6 (depends on 4)

The structure of claim 4, wherein each of the bottom electrode and the top electrode includes TaN, TIN, Ti/TIN, TaN/TIN, Ta or a combinations thereof.

### Claim 7 (depends on 1)

The structure of claim 1, further comprising:
in the memory device region and not in the logic device region, an aluminum oxide layer between the dielectric barrier layer and the first dielectric layer.

### Claim 8 (depends on 1)

The structure of claim 1, wherein top surfaces of the extreme low-k dielectric layer, the MTJ devices, and the conductive feature are co-planar.

### Claim 9

A structure having a memory device region and a logic device region, the structure comprising:
a first metal layer extending across an interface between the memory device region and the logic device region;
a dielectric barrier layer over the first metal layer in both the memory device region and the logic device region;
a first dielectric layer over the dielectric barrier layer in the memory device region;
magnetic tunneling junction (MTJ) stacks over the first dielectric layer in the memory device region;
dielectric spacers extending along sidewalls of the MTJ stacks;
a second dielectric layer over the first dielectric layer and between the dielectric spacers in the memory device region, wherein the second dielectric layer includes a silicon nitride based dielectric material;
MTJ vias connecting the MTJ stacks to the first metal layer, the MTJ vias isolated from each other by the first dielectric layer;
an extreme low-k dielectric layer over the dielectric barrier layer in the logic device region and physically contacting sidewalls of the first and second dielectric layers; and
a conductive feature in the logic device region, penetrating the extreme low-k dielectric layer and the dielectric barrier layer, and electrically connecting to the first metal layer.

### Claim 10 (depends on 9)

The structure of claim 9, wherein the first dielectric layer includes a dielectric material that is different from that of the second dielectric layer.

### Claim 11 (depends on 9)

The structure of claim 9, wherein the extreme low-k dielectric layer directly lands on the dielectric barrier layer.

### Claim 12 (depends on 9)

The structure of claim 9, wherein a portion of the extreme low-k dielectric layer is directly over the second dielectric layer in the memory device region.

### Claim 13 (depends on 9)

The structure of claim 9, wherein the extreme low-k dielectric layer has a lower dielectric constant than that of the first and second dielectric layers.

### Claim 14 (depends on 9)

The structure of claim 9, further comprising spacer protection layers along sidewalls of the MTJ stacks and along sidewalls of the first dielectric layer.

### Claim 15 (depends on 9)

The structure of claim 9, wherein the dielectric spacers include an outer protection layer that interfaces with the second dielectric layer, the outer protection layer having a metal oxide material.

### Claim 16 (depends on 9)

The structure of claim 9, wherein the second dielectric layer has a higher dielectric constant than the first dielectric layer, and the first dielectric layer has a higher dielectric constant than the extreme low-k dielectric layer.

### Claim 17

A structure having a memory device region and a logic device region, the structure comprising:
a first metal layer extending across an interface between the memory device region and the logic device region;
a dielectric barrier layer over the first metal layer in both the memory device region and the logic device region;
a low-k dielectric layer over the dielectric barrier layer in the memory device region and not in the logic device region;
multiple magnetic tunneling junction (MTJ) devices in the memory device region and not in the logic device region, each of the MTJ devices having an MTJ stack sandwiched between a top and a bottom electrode, wherein the MTJ devices are disposed over the first metal layer, the dielectric barrier layer, and the low-k dielectric layer;
multiple MTJ vias penetrating through the low-k dielectric layer and the dielectric barrier layer to connect the MTJ devices to the first metal layer;
a silicon nitride layer over the low-k dielectric layer in the memory device region and not in the logic device region, the silicon nitride layer surrounding the multiple MTJ devices;
an extreme low-k dielectric layer over the dielectric barrier layer in the logic device region, wherein a portion of the extreme low-k dielectric layer is directly on a top surface of the silicon nitride layer; and
a conductive feature in the logic device region, penetrating the extreme low-k dielectric layer and the dielectric barrier layer, and electrically connecting to the first metal layer.

### Claim 18 (depends on 17)

The structure of claim 17, wherein the low-k dielectric layer and the extreme low-k dielectric layer include different material compositions.

### Claim 19 (depends on 18)

The structure of claim 18, wherein the extreme low-k dielectric layer includes porous carbon doped silicon dioxide.

### Claim 20 (depends on 17)

The structure of claim 17, wherein the extreme low-k dielectric layer surrounds and directly contacts each top electrode of each of the MTJ devices.