# US 12,193,290 B2 · Display substrate, preparation method thereof, and display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,193,290 B2 - Document ID: US12193290B2 - Status: Granted - Kind: B2 - Application number: 17/629,772 - Filed: 2021-04-30 - Published: 2023-05-25 - Granted: 2025-01-07 - Earliest claimed: 2021-01-29 - Assignees: Chengdu Boe Optoelectronics Technology Co., Ltd.; Boe Technology Group Co., Ltd. - Applicants: Chengdu BOE Optoelectronics Technology Co., Ltd.; BOE Technology Group Co., Ltd. - Inventors: Yuanjie Xu; Benlian Wang; Lili Du; Zhenhua Zhang; Yuxin Zhang; Pan Xu - Web page: https://patentgrep.com/patent/US12193290B2 ## CPC - G09G 3/3241: the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror - G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element - H10K 59/1201: {Manufacture or treatment} - H10K 59/1213: {the pixel elements being TFTs} - H10K 59/1216: {the pixel elements being capacitors} - H10K 59/131: Interconnections, e.g. wiring lines or terminals - G09G 2300/0426: Layout of electrodes and connections - G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing - G09G 2300/0842: forming a memory circuit, e.g. a dynamic memory with one capacitor - G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes - G09G 2310/0251: Precharge or discharge of pixel before applying new pixel voltage - G09G 2310/061: for resetting or blanking - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2320/0204: Compensation of DC component across the pixels in flat panels - H10K 59/1315: {comprising structures specially adapted for lowering the resistance} - H10K 59/35: comprising red-green-blue [RGB] subpixels - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES ## Abstract Provided are a display substrate, a preparation method thereof, and a display device. The display substrate includes a display region and a bonding region on one side of the display region. The bonding region at least includes a lead area; the display region includes a plurality of data lines and a plurality of data fanout lines, the lead area includes a plurality of lead wires, and orthographic projections of the plurality of data lines and the plurality of data fanout lines on a plane of the display substrate are at least partially overlapped. At least one lead wire is connected to the data line through the data fanout line. In the lead area, an orthographic projection of any one of the lead wires on the plane of the display substrate and orthographic projections of other lead wires on the plane of the display substrate have no overlap region. ## Claims ### Claim 1 A display substrate, comprising: a display region and a bonding region on one side of the display region, wherein the bonding region at least comprises a lead area; the display region comprises a plurality of data lines and a plurality of data fanout lines, the lead area comprises a plurality of lead wires, and orthographic projections of the plurality of data lines and the plurality of data fanout lines on a plane of the display substrate are at least partially overlapped; at least one lead wire is connected to a data line through a data fanout line; and in the lead area, an orthographic projection of any one of the lead wires on the plane of the display substrate and orthographic projections of other lead wires on the plane of the display substrate have no overlap region, and wherein at least one data fanout line comprises a first line segment and a second line segment; a first end of the first line segment is connected to the lead wire, and a second end of the first line segment extends in a direction away from the lead area, to be connected to the second line segment; the second line segment comprises a plurality of sub-segments, the plurality of sub-segments are interwoven to form a plurality of grid patterns, the plurality of grid patterns are repeated and consecutively arranged in the first direction and/or the second direction, and at least one sub-segment is connected to the data line through a via; the second direction is intersected with the first direction, and the first direction is parallel to the data line. ### Claim 2 (depends on 1) The display substrate according to claim 1, wherein at least one lead wire is directly connected to the data line. ### Claim 3 (depends on 1) The display substrate according to claim 1, wherein a quantity of the data lines is greater than a quantity of the data fanout lines. ### Claim 4 (depends on 1) The display substrate according to claim 1, wherein the plurality of lead wires in the lead area have the same width, adjacent lead wires have the same spacing, the width and the spacing are dimensions in the second direction, the second direction is intersected with the first direction, and the first direction is parallel to the data line. ### Claim 5 (depends on 1) The display substrate according to claim 1, wherein in a direction parallel to the display substrate, the display substrate has a center line, the center line extends in a first direction and equally divides pixel columns of the display region, the first direction being parallel to the data lines; on a side of the center line, the plurality of data lines comprise a first data line group and a second data line group, and the plurality of lead wires comprise a first lead group and a second lead group; the first data line group comprises a first data line, a second data line, . . . , and an Mth data line that are arranged in sequence along a second direction, the second data line group is arranged on a side of the first data line group in the second direction, the second data line group comprises an (M+1)th data line, an (M+2)th data line, . . . , and an Nth data line that are arranged in sequence along the second direction, the second direction is intersected with the first direction; the first lead group comprises a first lead wire, a second lead wire, . . . , and an Mth lead wire that are arranged in sequence along an opposite direction of the second direction, the second lead group comprises an (M+1)th lead wire, an (M+2)th lead wire, . . . , and an Nth lead wire that are arranged in sequence along the second direction, the lead wires of the first lead group and the lead wires of the second lead group being alternately arranged; M, and N are positive integers greater than 2, and M is less than N; the lead wires in the first lead group are connected to the data lines in the first data line group through the data fanout lines, and the lead wires in the second lead group are directly connected to the data lines in the second data line group. ### Claim 6 (depends on 5) The display substrate according to claim 5, wherein in a direction perpendicular to the display panel, the display substrate comprises a first conductive layer, a second conductive layer, and a third conductive layer, and an insulating layer is arranged between the first conductive layer and the second conductive layer as well as between the second conductive layer and the third conductive layer; and the data lines and the data fanout lines are arranged in different conductive layers. ### Claim 7 (depends on 6) The display substrate according to claim 6, wherein the data fanout lines comprise odd data fanout lines and even data fanout lines, the odd data fanout lines are connected to the data lines in odd columns in the first data line group, and the even data fanout lines are connected to the data lines in even columns in the first data line group; and the odd data fanout lines and the even data fanout lines are arranged in different conductive layers. ### Claim 8 (depends on 7) The display substrate according to claim 7, wherein the lead wires comprise odd lead wires and even lead wires, the odd lead wires are connected to the data lines in the odd columns in the first data line group through the odd data fanout lines, or are directly connected to the data lines in odd columns in the second data line group; and the even lead wires are connected to the data lines in the even columns in the first data line group through the even data fanout lines, or are directly connected to the data lines in even columns in the second data line group; the odd lead wires and the odd data fanout lines are arranged in the same layer and are of an integrated structure connected to each other, and the even lead wires and the even data fanout lines are arranged in the same layer and are of an integrated structure connected to each other. ### Claim 9 (depends on 7) The display substrate according to claim 7, wherein the odd data fanout lines are arranged in the first conductive layer, the even data fanout lines are arranged in the second conductive layer, and the data lines are arranged in the third conductive layer; or, the even data fanout lines are arranged in the first conductive layer, the odd data fanout lines are arranged in the second conductive layer, and the data lines are arranged in the third conductive layer. ### Claim 10 (depends on 1) A display device, comprising the display substrate according to claim 1. ### Claim 11 A preparation method for a display substrate, wherein the display substrate comprises a display region and a bonding region on a side of the display region, the bonding region at least comprising a lead area; the preparation method comprises: forming a plurality of data lines and a plurality of data fanout lines in the display region, and forming a plurality of lead wires in the lead area, wherein orthographic projections of the plurality of data lines and the plurality of data fanout lines on a plane of the display substrate are at least partially overlapped; and at least one lead wire is connected to a data line through a data fanout line; wherein in the lead area, an orthographic projection of any one of the lead wires on the plane of the display substrate and orthographic projections of other lead wires on the plane of the display substrate have no overlap region, wherein at least one data fanout line comprises a first line segment and a second line segment; a first end of the first line segment is connected to the lead wire, and a second end of the first line segment extends in a direction away from the lead area, to be connected to the second line segment; the second line segment comprises a plurality of sub-segments, the plurality of sub-segments are interwoven to form a plurality of grid patterns, the plurality of grid patterns are repeated and consecutively arranged in the first direction and/or the second direction, and at least one sub-segment is connected to the data line through a via; the second direction is intersected with the first direction, and the first direction is parallel to the data line.