# US 12,193,271 B2 · Display apparatus and method of manufacturing the same

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- Number: US 12,193,271 B2
- Document ID: US12193271B2
- Status: Granted
- Kind: B2
- Application number: 17/715,553
- Filed: 2022-04-07
- Published: 2023-04-27
- Granted: 2025-01-07
- Earliest claimed: 2021-10-27
- Assignees: Samsung Display Co., Ltd.
- Applicants: Samsung Display Co., Ltd.
- Inventors: Dongmin Lee; Jaewoo Jeong; Janghyun Kim; Jongoh Seo; Byungsoo So
- Web page: https://patentgrep.com/patent/US12193271B2

## CPC

- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- H10K 59/1213: {the pixel elements being TFTs}
- H10K 71/00: Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10D 30/0314: {of lateral top-gate TFTs comprising only a single gate}
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 30/6731: {Top-gate only TFTs}
- H10D 30/6745: {Polycrystalline or microcrystalline silicon}
- H10D 86/0223: {comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials}
- H10D 86/421: {having a particular composition, shape or crystalline structure of the active layer}
- H10D 86/60: wherein the TFTs are in active matrices
- H10K 59/1201: {Manufacture or treatment}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

A display apparatus includes a substrate, a gate electrode overlapping the substrate, and a semiconductor layer positioned between the substrate and the gate electrode. The semiconductor layer includes a first layer and a second layer positioned between the first layer and the gate electrode. A hydrogen content of the first layer is greater than a hydrogen content of the second layer.

## Claims

### Claim 1

A method for manufacturing a display apparatus, the method comprising:
forming an amorphous silicon layer on a substrate;
heat-treating the amorphous silicon layer to form a heat-treated amorphous silicon layer;
doping the heat-treated amorphous silicon layer with hydrogen to form a hydrogen-doped amorphous silicon layer; and
crystallizing the hydrogen-doped amorphous silicon layer into a polycrystalline silicon layer by irradiating a laser to the hydrogen-doped amorphous silicon layer,
wherein the hydrogen-doped amorphous silicon layer includes a first portion and a second portion,
wherein the first portion is positioned between the substrate and the second portion, and
wherein a hydrogen content of the first portion is greater than a hydrogen content of the second portion.

### Claim 2 (depends on 1)

The method of claim 1, wherein
a deposition temperature for forming the amorphous silicon layer through deposition in the forming of the amorphous silicon layer on the substrate is in a range of 390° C. to 490° C.

### Claim 3 (depends on 1)

The method of claim 1, wherein
a heat treatment temperature in the heat-treating is in a range of 440° C. to 500° C.

### Claim 4 (depends on 1)

The method of claim 1, wherein
the heat-treating is performed for a period in a range of 300 seconds to 360 seconds.

### Claim 5 (depends on 1)

The method of claim 1, wherein
a hydrogen content of the heat-treated amorphous silicon layer is 3 at % or less.

### Claim 6 (depends on 1)

The method of claim 1, wherein
a dose amount of hydrogen in the doping is in a range of 1×1015 atom/cm3 to 1×1017 atom/cm3.

### Claim 7 (depends on 1)

The method of claim 1, wherein
an acceleration voltage in the doping is in a range of 3 keV to 10 keV.

### Claim 8 (depends on 1)

The method of claim 1, wherein
a thickness of the hydrogen-doped amorphous silicon layer in a direction perpendicular to the substrate is in a range of 450 Å to 500 Å.

### Claim 9 (depends on 8)

The method of claim 8, wherein
a thickness of the first portion in the direction perpendicular to the substrate is in a range of 150 Å to 170 Å.

### Claim 10 (depends on 1)

The method of claim 1, further comprising:
forming a semiconductor layer by patterning the polycrystalline silicon layer.

### Claim 11 (depends on 10)

The method of claim 10, wherein
a grain interface of polycrystalline silicon included in the semiconductor layer is oriented in a thickness direction of the semiconductor layer.

### Claim 12 (depends on 10)

The method of claim 10, wherein the semiconductor layer includes a first layer and a second layer,
wherein the first layer is positioned between the substrate and the second layer, and
wherein a hydrogen content of the first layer is greater than a hydrogen content of the second layer.

### Claim 13 (depends on 1)

The method of claim 1, further comprising:
after the crystallizing, forming a gate electrode that overlaps the polycrystalline silicon layer.