# US 12,193,243 B2 · Lateral multi-bit memory devices and methods of making the same

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- Number: US 12,193,243 B2
- Document ID: US12193243B2
- Status: Granted
- Kind: B2
- Application number: 17/650,084
- Filed: 2022-02-07
- Published: 2023-08-10
- Granted: 2025-01-07
- Earliest claimed: 2022-02-07
- Assignees: Globalfoundries Singapore Pte. Ltd.
- Applicants: GlobalFoundries Singapore Pte. Ltd.
- Inventors: Desmond Jia Jun Loy; Eng Huat Toh; Shyue Seng Tan
- Web page: https://patentgrep.com/patent/US12193243B2

## CPC

- H10B 63/82: {the switching components having a common active material layer}
- H10B 63/00: Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10N 70/011: {Manufacture or treatment of multistable switching devices}
- H10N 70/068: {by processes specially adapted for achieving sub-lithographic dimensions, e.g. using spacers}
- H10N 70/24: {based on migration or redistribution of ionic species, e.g. anions, vacancies}
- H10N 70/823: {adapted for essentially horizontal current flow, e.g. bridge type devices}
- H10N 70/828: {Current flow limiting means within the switching material region, e.g. constrictions}
- H10N 70/841: {Electrodes}
- H10N 70/8416: {adapted for supplying ionic species}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

The disclosed subject matter relates generally to structures, memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices having two resistive layers and a conductive layer arranged between two electrodes. The present disclosure provides a memory device including a first electrode above an interlayer dielectric region, a second electrode above the interlayer dielectric region, the second electrode is laterally adjacent to the first electrode, a conductive layer between the first electrode and the second electrode, in which the conductive layer is electrically isolated, a first resistive layer between the first electrode and the conductive layer, and a second resistive layer between the second electrode and the conductive layer.

## Claims

### Claim 1

A memory device comprising:
a first electrode above an interlayer dielectric region;
a second electrode above the interlayer dielectric region, the second electrode is laterally adjacent to the first electrode;
a conductive layer between the first electrode and the second electrode, wherein the conductive layer is electrically isolated;
a first resistive layer between the first electrode and the conductive layer;
a second resistive layer between the second electrode and the conductive layer, the second resistive layer has a vertical portion and a horizontal portion, the horizontal portion having an upper surface, the vertical portion having a side surface, the upper surface of the horizontal portion joins the side surface of the vertical portion to provide a corner in the second resistive layer; and
a spacer element between the second electrode and the second resistive layer, the spacer element covers the corner in the second resistive layer.

### Claim 2 (depends on 1)

The device of claim 1, further comprising an oxygen scavenging layer between the second electrode and the second resistive layer, wherein the oxygen scavenging layer is in direct contact with the second electrode.

### Claim 3 (depends on 2)

The device of claim 2, wherein the oxygen scavenging layer is disposed directly on the second resistive layer and the spacer element.

### Claim 4 (depends on 1)

The device of claim 1, further comprising an oxygen scavenging layer between the first electrode and the first resistive layer, wherein the oxygen scavenging layer is in direct contact with the first electrode.

### Claim 5 (depends on 1)

The device of claim 1, further comprising an oxygen scavenging layer between the conductive layer and the first resistive layer, wherein the oxygen scavenging layer is in direct contact with the conductive layer.

### Claim 6 (depends on 1)

The device of claim 1, further comprising an oxygen scavenging layer between the conductive layer and the second resistive layer, wherein the oxygen scavenging layer is in direct contact with the conductive layer.

### Claim 7 (depends on 1)

The device of claim 1, wherein the first resistive layer has a vertical portion and a horizontal portion, and wherein the first electrode has a side surface and the vertical portion of the first resistive layer is positioned over the side surface of the first electrode.

### Claim 8 (depends on 7)

The device of claim 7, wherein the conductive layer is positioned over the first resistive layer, the second resistive layer is positioned over the conductive layer, and the second electrode is positioned over the second resistive layer.

### Claim 9

A memory device comprising:
a first electrode above an interlayer dielectric region;
a second electrode above the interlayer dielectric region, the second electrode is laterally adjacent to the first electrode;
a conductive layer between the first electrode and the second electrode, wherein the conductive layer is electrically isolated;
a first resistive layer between the first electrode and the conductive layer, the first resistive layer has a vertical portion and a horizontal portion, the horizontal portion having an upper surface, the vertical portion having a side surface, the upper surface of the horizontal portion joins the side surface of the vertical portion to provide a corner in the first resistive layer;
a second resistive layer between the second electrode and the conductive layer; and
a spacer element between the conductive layer and the first resistive layer, wherein the spacer element covers the corner in the first resistive layer.

### Claim 10 (depends on 9)

The device of claim 9, further comprising an oxygen scavenging layer between the second electrode and the second resistive layer, wherein the oxygen scavenging layer is in direct contact with the second electrode.

### Claim 11 (depends on 9)

The device of claim 9, further comprising an oxygen scavenging layer between the first electrode and the first resistive layer, wherein the oxygen scavenging layer is in direct contact with the first electrode.

### Claim 12 (depends on 9)

The device of claim 9, further comprising an oxygen scavenging layer between the conductive layer and the first resistive layer, wherein the oxygen scavenging layer is in direct contact with the conductive layer.

### Claim 13 (depends on 12)

The device of claim 12, wherein the oxygen scavenging layer is disposed directly on the first resistive layer and the spacer element.

### Claim 14 (depends on 9)

The device of claim 9, further comprising an oxygen scavenging layer between the conductive layer and the second resistive layer, wherein the oxygen scavenging layer is in direct contact with the conductive layer.

### Claim 15

A memory device comprising:
a first electrode above an interlayer dielectric region;
a second electrode above the interlayer dielectric region, the second electrode is laterally adjacent to the first electrode;
a conductive layer between the first electrode and the second electrode, the conductive layer has a vertical portion and a horizontal portion, the horizontal portion having an upper surface, the vertical portion having a side surface, the upper surface of the horizontal portion joins the side surface of the vertical portion to provide a corner in the conductive layer, wherein the conductive layer is electrically isolated;
a first resistive layer between the first electrode and the conductive layer;
a second resistive layer between the second electrode and the conductive layer; and
a spacer element between the conductive layer and the second resistive layer, wherein the spacer element covers the corner in the conductive layer.

### Claim 16 (depends on 15)

The device of claim 15, further comprising an oxygen scavenging layer between the second electrode and the second resistive layer, wherein the oxygen scavenging layer is in direct contact with the second electrode.

### Claim 17 (depends on 15)

The device of claim 15, further comprising an oxygen scavenging layer between the first electrode and the first resistive layer, wherein the oxygen scavenging layer is in direct contact with the first electrode.

### Claim 18 (depends on 15)

The device of claim 15, further comprising an oxygen scavenging layer between the conductive layer and the first resistive layer, wherein the oxygen scavenging layer is in direct contact with the conductive layer.

### Claim 19 (depends on 15)

The device of claim 15, further comprising an oxygen scavenging layer between the conductive layer and the second resistive layer, wherein the oxygen scavenging layer is in direct contact with the conductive layer.

### Claim 20 (depends on 19)

The device of claim 19, wherein the second resistive layer is disposed directly on the oxygen scavenging layer and the spacer element.