# US 12,193,236 B2 · Memory device and electronic device

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- Number: US 12,193,236 B2
- Document ID: US12193236B2
- Status: Granted
- Kind: B2
- Application number: 17/772,280
- Filed: 2020-11-13
- Published: 2022-11-24
- Granted: 2025-01-07
- Earliest claimed: 2019-11-26
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Hitoshi Kunitake; Satoru Ohshita; Kazuki Tsuda; Tatsuya Onuki
- Web page: https://patentgrep.com/patent/US12193236B2

## CPC

- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- H10B 43/40: characterised by the peripheral circuit region
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/60: wherein the TFTs are in active matrices
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A memory device with a small number of wirings using a NAND flash memory having a three-dimensional structure with a large number of stacked memory cell layers is provided. A decoder is formed using an OS transistor. An OS transistor can be formed by a method such as a thin film method, whereby the decoder can be provided to be stacked above the NAND flash memory having a three-dimensional structure. This can reduce the number of wirings provided substantially perpendicular to the memory cell layers.

## Claims

### Claim 1

A memory device comprising:
a first layer;
a second layer; and
a third layer,
wherein a decoder is provided in the first layer,
wherein a memory cell portion is provided in the second layer,
wherein a circuit is provided in the third layer,
wherein the circuit is configured to control the decoder and the memory cell portion,
wherein the decoder is configured to select or deselect part of the memory cell portion,
wherein at least part of the second layer is provided to be stacked above the third layer, and
wherein at least part of the first layer is provided to be stacked above the second layer.

### Claim 2 (depends on 1)

The memory device according to claim 1,
wherein the third layer comprises a single crystal silicon substrate,
wherein the circuit comprises a first transistor formed using the single crystal silicon substrate,
wherein the decoder comprises a second transistor, and
wherein the second transistor comprises a metal oxide in a channel formation region.

### Claim 3 (depends on 1)

The memory device according to claim 1,
wherein the third layer comprises an SOI substrate,
wherein the circuit comprises a first transistor formed using the SOI substrate,
wherein the decoder comprises a second transistor, and
wherein the second transistor comprises a metal oxide in a channel formation region.

### Claim 4 (depends on 1)

An electronic device comprising the memory device according to claim 1.

### Claim 5

A memory device comprising:
a first layer;
a second layer; and
a third layer,
wherein a decoder is provided in the first layer,
wherein a memory cell portion is provided in the second layer,
wherein a circuit is provided in the third layer,
wherein the circuit is configured to control the decoder and the memory cell portion,
wherein the circuit is configured to output a selection signal to the decoder,
wherein the memory cell portion comprises a NAND memory element having a three-dimensional structure,
wherein the decoder is configured to output a signal for selecting or deselecting part of the memory cell portion to the memory cell portion in accordance with the selection signal,
wherein at least part of the second layer is provided to be stacked above the third layer, and
wherein at least part of the first layer is provided to be stacked above the second layer.

### Claim 6 (depends on 5)

The memory device according to claim 5,
wherein the third layer comprises a single crystal silicon substrate,
wherein the circuit comprises a first transistor formed using the single crystal silicon substrate,
wherein the decoder comprises a second transistor, and
wherein the second transistor comprises a metal oxide in a channel formation region.

### Claim 7 (depends on 5)

The memory device according to claim 5,
wherein the third layer comprises an SOI substrate,
wherein the circuit comprises a first transistor formed using the SOI substrate,
wherein the decoder comprises a second transistor, and
wherein the second transistor comprises a metal oxide in a channel formation region.

### Claim 8 (depends on 5)

An electronic device comprising the memory device according to claim 5.