# US 12,193,234 B2 · Semiconductor memory device and manufacturing method of semiconductor memory device

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- Number: US 12,193,234 B2
- Document ID: US12193234B2
- Status: Granted
- Kind: B2
- Application number: 17/513,494
- Filed: 2021-10-28
- Published: 2022-11-10
- Granted: 2025-01-07
- Earliest claimed: 2021-05-06
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Byung Wook Bae
- Web page: https://patentgrep.com/patent/US12193234B2

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/40: characterised by the peripheral circuit region
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 90/00: Package configurations
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 80/732: {having shape changed during the connecting}
- H10W 90/792: {between multiple chips}
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor memory device includes a bit line, a common source pattern above the bit line, a channel layer in contact with the common source pattern, the channel layer extending toward the bit line, and a filling insulating layer disposed between the bit line and the common source pattern, the filling insulating layer surrounding a first part of the channel layer. The semiconductor memory device also includes a gate stack structure disposed between the bit line and the filling insulating layer, the gate stack structure surrounding a second part of the channel layer. The semiconductor memory device further includes a first etch stop pattern on a sidewall of the filling insulating layer, a second etch stop pattern between the first etch stop pattern and the filling insulating layer, and a memory pattern between the gate stack structure and the channel layer.

## Claims

### Claim 1

A semiconductor memory device comprising:
a bit line;
a common source pattern above the bit line;
a channel layer in contact with the common source pattern, the channel layer extending toward the bit line;
a filling insulating layer disposed between the bit line and the common source pattern, the filling insulating layer surrounding a first part of the channel layer;
a gate stack structure disposed between the bit line and the filling insulating layer, the gate stack structure surrounding a second part of the channel layer;
a first etch stop pattern on a sidewall of the filling insulating layer;
a second etch stop pattern between the first etch stop pattern and the filling insulating layer; and
a memory pattern between the gate stack structure and the channel layer,
wherein a first sidewall of the second etch stop pattern which is in contact with the filling insulating layer and a second sidewall of the second etch stop pattern which is in contact with the first etch stop pattern are inclined in the same direction.

### Claim 2 (depends on 1)

The semiconductor memory device of claim 1, wherein the filling insulating layer includes a material having an etch selectivity with respect to the second etch stop pattern.

### Claim 3 (depends on 2)

The semiconductor memory device of claim 2, wherein the filling insulating layer includes at least one of a nitride layer and an oxide layer.

### Claim 4 (depends on 2)

The semiconductor memory device of claim 2, wherein the second etch stop pattern includes a silicon layer.

### Claim 5 (depends on 1)

The semiconductor memory device of claim 1, wherein the first etch stop pattern includes an insulating material having an etch selectivity with respect to a semiconductor wafer.

### Claim 6 (depends on 5)

The semiconductor memory device of claim 5, wherein the first etch stop pattern includes an oxide layer.

### Claim 7 (depends on 1)

The semiconductor memory device of claim 1, wherein the first etch stop pattern and the second etch stop pattern are disposed at a level where the filling insulating layer is disposed.

### Claim 8 (depends on 1)

The semiconductor memory device of claim 1, wherein the gate stack structure extends to overlap with the first etch stop pattern and the second etch stop pattern.

### Claim 9 (depends on 1)

The semiconductor memory device of claim 1, further comprising a semiconductor pattern on a sidewall of the first etch stop pattern.

### Claim 10 (depends on 9)

The semiconductor memory device of claim 9, wherein the gate stack structure extends to be overlapped by the semiconductor pattern.

### Claim 11 (depends on 1)

The semiconductor memory device of claim 1, further comprising a core insulating pattern disposed in a central region of the channel layer,
wherein the channel layer extends between the core insulating pattern and the common source pattern.

### Claim 12 (depends on 11)

The semiconductor memory device of claim 11, wherein:
the common source pattern includes a doped semiconductor layer in contact with the channel layer; and
the doped semiconductor layer overlaps the core insulating pattern with the channel layer interposed between the doped semiconductor layer and the core insulating pattern.

### Claim 13 (depends on 1)

The semiconductor memory device of claim 1, wherein the first etch stop pattern and the second etch stop pattern are disposed at the same level.

### Claim 14 (depends on 1)

The semiconductor memory device of claim 1, wherein the first sidewall and the second sidewall are disposed at the same level.

### Claim 15 (depends on 1)

The semiconductor memory device of claim 1, wherein the first sidewall and the second sidewall face opposite directions.