# US 12,193,230 B2 · Three-dimensional memory device and method for forming the same

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- Number: US 12,193,230 B2
- Document ID: US12193230B2
- Status: Granted
- Kind: B2
- Application number: 17/459,456
- Filed: 2021-08-27
- Published: 2022-12-01
- Granted: 2025-01-07
- Earliest claimed: 2021-05-28
- Assignees: Yangtze Memory Technologies Co., Ltd.
- Applicants: Yangtze Memory Technologies Co., Ltd.
- Inventors: Yuancheng Yang; Bingjie Yan; Di Wang; Cuicui Kong; Wenxi Zhou
- Web page: https://patentgrep.com/patent/US12193230B2

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A three-dimensional (3D) memory device includes a doped semiconductor layer, a stack structure, and a channel structure. The stack structure includes interleaved conductive layers and dielectric layers formed on the doped semiconductor layer. The conductive layers include a plurality of word lines, and a drain select gate line. The channel structure extends through the stack structure along a first direction and is in contact with the doped semiconductor layer. The drain select gate line includes a first dielectric layer in contact with the channel structure, and a first polysilicon layer in contact with the first dielectric layer.

## Claims

### Claim 1

A three-dimensional (3D) memory device, comprising:
a doped semiconductor layer;
a stack structure comprising interleaved conductive layers and dielectric layers formed on the doped semiconductor layer, the conductive layers comprising a plurality of word lines, and a drain select gate line; and
a channel structure comprising a semiconductor channel and a memory film over the semiconductor channel, the channel structure extending through the stack structure along a first direction and in contact with the doped semiconductor layer,
wherein the drain select gate line comprises a first dielectric layer in direct contact with the semiconductor channel of the channel structure, and a first polysilicon layer in contact with the first dielectric layer.

### Claim 2 (depends on 1)

The 3D memory device of claim 1, wherein the memory film comprises:
a tunneling layer over the semiconductor channel;
a storage layer over the tunneling layer; and
a blocking layer over the storage layer,
wherein the semiconductor channel, the tunneling layer, the storage layer, and the blocking layer are stacked along a second direction perpendicular to the first direction.

### Claim 3 (depends on 2)

The 3D memory device of claim 2, wherein the plurality of word lines are in contact with the blocking layer.

### Claim 4 (depends on 2)

The 3D memory device of claim 2, wherein each of the plurality of word lines comprises a gate dielectric layer, an adhesion layer, and a conductive layer, wherein the gate dielectric layer is in contact with the blocking layer.

### Claim 5 (depends on 1)

The 3D memory device of claim 1, wherein the conductive layers further comprise a source select gate line, and the source select gate line comprises a second dielectric layer in contact with the channel structure and a second polysilicon layer in contact with the second dielectric layer.

### Claim 6 (depends on 5)

The 3D memory device of claim 5, wherein the channel structure further comprises:
a channel contact formed beneath the semiconductor channel, and in contact with the doped semiconductor layer,
wherein the source select gate line is in direct contact with the channel contact.

### Claim 7 (depends on 1)

The 3D memory device of claim 1, wherein:
the plurality of word lines comprise a first word line comprising a first gate dielectric layer, and a second word line comprising a second gate dielectric layer; and
the first gate dielectric layer and the second gate dielectric layer are connected.

### Claim 8 (depends on 7)

The 3D memory device of claim 7, wherein:
the first gate dielectric layer and the second gate dielectric layer comprise a same material.

### Claim 9 (depends on 1)

The 3D memory device of claim 1, wherein:
the memory film comprises a blocking layer; and
one word line of the plurality of word lines comprises a gate dielectric layer, the gate dielectric layer being in contact with the blocking layer.

### Claim 10 (depends on 1)

The 3D memory device of claim 1, wherein:
the memory film comprises a blocking layer; and
the blocking layer is discontinuous at the drain select gate line.

### Claim 11 (depends on 1)

The 3D memory device of claim 1, wherein the memory film comprises:
a tunneling layer over the semiconductor channel;
a storage layer over the tunneling layer; and
a blocking layer over the storage layer,
wherein the drain select gate line extends in a second direction perpendicular to the first direction to break the tunnel layer, the storage layer, and the blocking layer to be in direct contact with the semiconductor channel.

### Claim 12

A three-dimensional (3D) memory device, comprising:
a doped semiconductor layer;
a stack structure comprising interleaved conductive layers and dielectric layers formed on the doped semiconductor layer, the conductive layers comprising a source select gate line, and a plurality of word lines; and
a channel structure comprising a channel contact formed at a bottom region of the channel structure, the channel structure extending through the stack structure along a first direction and in contact with the doped semiconductor layer,
wherein the source select gate line comprises a first dielectric layer in direct contact with the channel contact of the channel structure, and a first polysilicon layer in contact with the first dielectric layer.

### Claim 13 (depends on 12)

The 3D memory device of claim 12, wherein the conductive layers further comprise a drain select gate line, and the drain select gate line comprises a second dielectric layer in contact with the channel structure and a second polysilicon layer in contact with the second dielectric layer.

### Claim 14 (depends on 13)

The 3D memory device of claim 13, wherein the channel structure further comprises:
a semiconductor channel;
a tunneling layer over the semiconductor channel;
a storage layer over the tunneling layer; and
a blocking layer over the storage layer,
wherein the second dielectric layer of the drain select gate line is in direct contact with the semiconductor channel.

### Claim 15 (depends on 14)

The 3D memory device of claim 14, wherein the semiconductor channel, the tunneling layer, the storage layer, and the blocking layer are stacked along a second direction perpendicular to the first direction.

### Claim 16 (depends on 12)

The 3D memory device of claim 12, wherein:
the channel contact comprises silicon.

### Claim 17 (depends on 12)

The 3D memory device of claim 12, wherein:
a material of the source select gate line is different from a material of each of the plurality of word lines.

### Claim 18

A three-dimensional (3D) memory device, comprising:
a doped semiconductor layer;
a stack structure comprising interleaved conductive layers and dielectric layers formed over the doped semiconductor layer, the conductive layers comprising a plurality of word lines and a drain select gate line; and
a channel structure comprising a semiconductor channel and a memory film over the semiconductor channel, and extending through the stack structure along a first direction to be in contact with the doped semiconductor layer,
wherein:
the drain select gate line extends in a second direction perpendicular to the first direction and extends through a first portion of the memory film to be in direct contact with the semiconductor channel; and
one word line of the plurality of word lines extends in the second direction and is in contact with a second portion of the memory film.

### Claim 19 (depends on 18)

The 3D memory device of claim 18, wherein:
the memory film comprises a tunneling layer, a storage layer, and a blocking layer arranged in this order from the semiconductor channel; and
the drain select gate line penetrates the tunneling layer, the storage layer, and the blocking layer to be in direct contact with the semiconductor channel.

### Claim 20 (depends on 18)

The 3D memory device of claim 18, wherein:
the memory film comprises a tunneling layer, a storage layer, and a blocking layer arranged in this order from the semiconductor channel; and
the tunneling layer, the storage layer, and the blocking layer are discontinuous at the drain select gate line.