# US 12,193,227 B2 · Etch method for opening a source line in flash memory

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- Number: US 12,193,227 B2
- Document ID: US12193227B2
- Status: Granted
- Kind: B2
- Application number: 18/353,308
- Filed: 2023-07-17
- Published: 2023-11-09
- Granted: 2025-01-07
- Earliest claimed: 2019-08-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Yong-Sheng Huang; Ming Chyi Liu; Chih-Pin Huang
- Web page: https://patentgrep.com/patent/US12193227B2

## CPC

- H10B 41/30: characterised by the memory core region
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/683: {programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling}
- H10D 30/6892: {having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10P 50/264: {by chemical means}
- H10P 50/283: {by chemical means}
- H10P 50/73: {using masks for insulating materials}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/067: {by modifying the pattern of conductive parts}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/43: Layouts of interconnections
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Various embodiments of the present disclosure are directed towards a method for opening a source line in a memory device. An erase gate line (EGL) and the source line are formed elongated in parallel. The source line underlies the EGL and is separated from the EGL by a dielectric layer. A first etch is performed to form a first opening through the EGL and stops on the dielectric layer. A second etch is performed to thin the dielectric layer at the first opening, wherein the first and second etches are performed with a common mask in place. A silicide process is performed to form a silicide layer on the source line at the first opening, wherein the silicide process comprises a third etch with a second mask in place and extends the first opening through the dielectric layer. A via is formed extending through the EGL to the silicide layer.

## Claims

### Claim 1

A memory device comprising:
a substrate;
an erase gate line and a source line elongated in parallel, wherein the erase gate line has a break separating the erase gate line into a pair of erase gate segments, and wherein the source line underlies the erase gate line in the substrate;
a pair of floating gates overlying the substrate and including a first floating gate, wherein the pair of floating gates are adjacent to, and respectively on opposite sides of, the break;
a sidewall spacer directly between and spaced from the pair of floating gates, wherein a bottom surface of the sidewall spacer is at an elevation that is closer to an elevation at a bottom surface of the first floating gate than to an elevation at a top surface of the first floating gate and an elevation at a top surface of the substrate;
a contact etch stop layer having a U-shaped profile and directly contacting the sidewall spacer at the break; and
a contact via extending through the contact etch stop layer at the break.

### Claim 2 (depends on 1)

The memory device according to claim 1, wherein the bottom surface of the sidewall spacer is level with the first floating gate.

### Claim 3 (depends on 1)

The memory device according to claim 1, wherein the sidewall spacer borders and is non-overlapping with the first floating gate when viewed top down.

### Claim 4 (depends on 1)

The memory device according to claim 1, wherein the bottom surface of the sidewall spacer faces the substrate and is slanted relative to a bottom surface of the substrate.

### Claim 5 (depends on 1)

The memory device according to claim 1, further comprising:
a control gate line overlying the first floating gate and elongated in parallel with the erase gate line and the source line, wherein a top surface of the sidewall spacer is recessed relative to a top surface of the control gate line.

### Claim 6 (depends on 1)

The memory device according to claim 1, wherein the sidewall spacer comprises silicon nitride.

### Claim 7 (depends on 1)

The memory device according to claim 1, further comprising:
a control gate line overlying the first floating gate and elongated in parallel with the erase gate line and the source line, wherein a top surface of the sidewall spacer is level with the control gate line.

### Claim 8

A memory device comprising:
a substrate;
an erase gate line and a control gate line elongated in parallel, wherein the erase gate line has a break separating the erase gate line into a pair of erase gate segments;
a floating gate underlying the control gate line at the break; and
a sidewall spacer that extends along and is spaced from a sidewall of the floating gate, and further has a height less than a separation between a bottom surface of the floating gate and a top surface of the control gate line, at the break.

### Claim 9 (depends on 8)

The memory device according to claim 8, further comprising:
a dielectric layer separating the floating gate from the substrate, wherein the sidewall spacer is a different type of dielectric material than the dielectric layer.

### Claim 10 (depends on 8)

The memory device according to claim 8, further comprising:
a source line in the substrate, wherein the source line underlies and is elongated in parallel with the erase gate line, and wherein the sidewall spacer is spaced from the source line.

### Claim 11 (depends on 8)

The memory device according to claim 8, further comprising:
an etch stop layer lining the sidewall spacer at the break, wherein a bottom surface of the etch stop layer is recessed relative to a bottom surface of the sidewall spacer; and
a contact via extending through the etch stop layer.

### Claim 12 (depends on 8)

The memory device according to claim 8, wherein a top edge of the sidewall spacer is level with the control gate line.

### Claim 13 (depends on 8)

The memory device according to claim 8, wherein a bottom edge of the sidewall spacer is elevated relative to a top-surface portion of the substrate at the break, and wherein the top-surface portion underlies the floating gate.

### Claim 14 (depends on 8)

The memory device according to claim 8, further comprising:
a silicide layer on the substrate at the break, wherein a top surface of the silicide layer has a width-wise center and a periphery in a cross-sectional plane that extends in a direction along which the erase gate line and the control gate line are elongated in parallel, and wherein the width-wise center is elevated relative to the periphery.

### Claim 15

A memory device comprising:
a substrate;
a control gate line and a select gate line elongated in parallel, wherein the select gate line has a break separating the select gate line into a pair of select gate segments, and wherein the control gate line has a pad at the break; and
a trench isolation structure underlying the control gate line and the select gate line;
wherein the pad has a first side and a second side respectively facing the pair of select gate segments on opposite sides of the pad, and wherein the trench isolation structure has a recess that wraps around the pad from the first side to the second side when viewed top down.

### Claim 16 (depends on 15)

The memory device according to claim 15, wherein the pad overlies a semiconductor mesa of the substrate, and wherein the trench isolation structure extends in a closed path around the semiconductor mesa.

### Claim 17 (depends on 16)

The memory device according to claim 16, wherein the recess is on four sides of the semiconductor mesa.

### Claim 18 (depends on 15)

The memory device according to claim 15, wherein the recess is localized to between the pair of select gate segments.

### Claim 19 (depends on 15)

The memory device according to claim 15, wherein a portion of the trench isolation structure in the recess is recessed relative to another portion of the trench isolation structure masked by the pad.

### Claim 20 (depends on 15)

The memory device according to claim 15, further comprising:
an erase gate line elongated in parallel with the control gate line, wherein the erase gate line has another break separating the erase gate line into a pair of erase gate segments;
a floating gate underlying the control gate line at the other break; and
a sidewall spacer extending along and spaced from the floating gate at the other break, wherein a bottom surface of the sidewall spacer is elevated relative to a recessed surface of the trench isolation structure in the recess.