# US 12,193,225 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,193,225 B2 - Document ID: US12193225B2 - Status: Granted - Kind: B2 - Application number: 17/369,453 - Filed: 2021-07-07 - Published: 2022-07-14 - Granted: 2025-01-07 - Earliest claimed: 2021-01-12 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Takatoshi Minamoto; Sho Tokairin; Yoshinao Suzuki - Web page: https://patentgrep.com/patent/US12193225B2 ## CPC - G11C 16/30: Power supply circuits - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - H10B 43/10: characterised by the top-view layout - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions - G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)} - G11C 5/148: {Details of power up or power down circuits, standby circuits or recovery circuits} - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A semiconductor device has a first conductivity type semiconductor substrate. A second conductivity type first impurity diffusion layer is disposed in a surface region of the semiconductor substrate. A resistance element is configured with a first conductivity type second impurity diffusion layer disposed in the first impurity diffusion layer in the surface region of the semiconductor substrate. In a transistor, a gate is connected to an input portion of the resistance element, a source is connected to the first impurity diffusion layer, and a drain is connected to a voltage source higher than the voltage of the input portion. A current source is connected to the source. ## Claims ### Claim 1 A semiconductor device comprising: a first conductivity type semiconductor substrate; a second conductivity type first impurity diffusion layer disposed in a surface region of the semiconductor substrate; a first resistance element, including a first conductivity type second impurity diffusion layer and having an input portion, disposed in the second conductivity type first impurity diffusion layer; a second resistance element, including a first conductivity type third impurity diffusion layer that is separated from the second conductivity type first impurity diffusion layer; a transistor that is out from the second conductivity type first impurity diffusion layer and the first conductivity type third impurity diffusion layer including: a gate connected to the input portion, a source connected to the second conductivity type first impurity diffusion layer, and a drain connected to a voltage source, the voltage source having a voltage higher than a voltage of the input portion; and a current source connected to the source, wherein the first resistance element and the second resistance element are in series between the input portion and an output portion, the output portion having a voltage lower than the voltage of the voltage source. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the transistor includes a field effect transistor. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the semiconductor device includes a memory device. ### Claim 4 (depends on 3) The semiconductor device according to claim 3, further comprising a stacked body, the stacked body including alternating layers of insulating layers and conducting layers disposed above the transistor. ### Claim 5 (depends on 4) The semiconductor device according to claim 4, wherein the insulating layers contain silicon oxide and conducting layers contain tungsten. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, further including an interlayer insulating film disposed over the transistor and the resistance element. ### Claim 7 (depends on 6) The semiconductor device according to claim 6, wherein the interlayer insulating film contains silicon oxide. ### Claim 8 (depends on 6) The semiconductor device according to claim 6, further including wiring disposed in the interlayer insulating film and electrically connected to the transistor. ### Claim 9 (depends on 1) The semiconductor device according to claim 1, wherein the transistor includes a depression type transistor. ### Claim 10 (depends on 9) The semiconductor device according to claim 9, wherein the transistor has a negative threshold voltage. ### Claim 11 (depends on 1) The semiconductor device according to claim 1, wherein a plurality of the resistance elements are disposed in the surface region of the semiconductor substrate, and the plurality of resistance elements are connected in series. ### Claim 12 (depends on 11) The semiconductor device according to claim 11, further including shallow trench isolation between the plurality of resistance elements. ### Claim 13 (depends on 11) The semiconductor device according to claim 11, further including a plurality of transistors arranged to respectively bias the plurality of resistance elements. ### Claim 14 (depends on 1) The semiconductor device according to claim 1, wherein the source and the drain of the transistor are of the second conductivity type. ### Claim 15 (depends on 1) The semiconductor device according to claim 1, wherein the second conductivity type first impurity diffusion layer has a voltage higher than the voltage of the input portion by an absolute value of a threshold voltage of the transistor.