# US 12,193,224 B2 · Memory device and method for manufacturing the same

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- Number: US 12,193,224 B2
- Document ID: US12193224B2
- Status: Granted
- Kind: B2
- Application number: 17/591,299
- Filed: 2022-02-02
- Published: 2022-08-04
- Granted: 2025-01-07
- Earliest claimed: 2021-02-04
- Assignees: Winbond Electronics Corp.
- Applicants: Winbond Electronics Corp.
- Inventors: Chun-Lin Li
- Web page: https://patentgrep.com/patent/US12193224B2

## CPC

- H10B 20/25: One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
- H10W 20/491: {Antifuses, i.e. interconnections changeable from non-conductive to conductive}
- H10B 20/60: {Peripheral circuit regions}
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A memory device includes a substrate and an eFuse structure. The substrate includes an array region and an eFuse region and the eFuse region of the substrate has an eFuse trench. The eFuse structure includes a first gate oxide layer, a plurality of doped regions, a dummy buried word line, and an eFuse gate electrode. The first gate oxide layer is conformally formed on a surface of the eFuse trench. The doped regions are respectively formed in the substrate on opposite sides outside the eFuse trench, and in contact with the first gate oxide layer. The dummy buried word line is formed on the first gate oxide layer. The eFuse gate electrode is formed on the dummy buried word line and in contact with the first gate oxide layer. The dummy buried word line is electrically isolated from the eFuse gate electrode.

## Claims

### Claim 1

A memory device, comprising:
a substrate having an array region and an electronic fuse (eFuse) region, wherein the eFuse region of the substrate has an eFuse trench; and
an eFuse structure, comprising:
a first gate oxide layer conformally formed on a surface of the eFuse trench;
a plurality of doped regions, respectively formed in the substrate on opposite sides outside the eFuse trench, wherein the plurality of doped regions are in contact with the first gate oxide layer;
a dummy buried word line formed on the first gate oxide layer; and
an eFuse gate electrode formed on the dummy buried word line and in contact with the first gate oxide layer, wherein the dummy buried word line is electrically isolated from the eFuse gate electrode.

### Claim 2 (depends on 1)

The memory device as claimed in claim 1, wherein the eFuse structure further comprises an insulating filling layer disposed between the dummy buried word line and the eFuse gate electrode, a portion of the eFuse gate electrode that contacts the first gate oxide layer has a first thickness D1, and each of the plurality of doped regions has a depth D2 greater than the first thickness D1.

### Claim 3 (depends on 2)

The memory device as claimed in claim 2, wherein a ratio of the depth D2 to the first thickness D1 (D2/D1) is in a range of 1.5 to 5.0.

### Claim 4 (depends on 1)

The memory device as claimed in claim 1, wherein the array region of the substrate has a word line trench, and the memory device further comprises:
a buried word line formed in the word line trench, wherein a top surface of the buried word line is higher than a top surface of the dummy buried word line, and
wherein the word line trench has a first width W1, the eFuse trench has a second width W2, and a ratio of the second width W2 to the first width W1 (W2/W1) is in a range of 2.0 to 5.0.

### Claim 5 (depends on 1)

The memory device as claimed in claim 1 further comprising a second gate oxide layer over the substrate, wherein the second gate oxide layer has an opening that exposes the eFuse gate electrode, and a width of the opening is less than a bottom width of the eFuse gate electrode.

### Claim 6 (depends on 5)

The memory device as claimed in claim 5, wherein a ratio of the width of the opening to the bottom width of the eFuse gate electrode is in a range of 0.1 to 0.9.

### Claim 7 (depends on 5)

The memory device as claimed in claim 5, wherein a top surface of the eFuse gate electrode is lower than or level with a top surface of the second gate oxide layer.

### Claim 8 (depends on 7)

The memory device as claimed in claim 7, wherein the top surface of the eFuse gate electrode is higher than or level with a top surface of each of the plurality of doped regions.

### Claim 9 (depends on 1)

The memory device as claimed in claim 1, further comprising:
an eFuse contact structure electrically connecting the eFuse gate electrode, wherein the eFuse contact structure comprises:
a metal silicide layer on the eFuse gate electrode;
a metal layer on the metal silicide layer; and
a conductive layer on the metal layer,
wherein a width of the conductive layer is less than or equal to a width of the metal layer.

### Claim 10

A method for manufacturing a memory device, comprising:
providing a substrate, wherein the substrate has an array region and an eFuse region;
forming an eFuse structure in the eFuse region of the substrate, wherein forming the eFuse structure comprises:
forming an eFuse trench in the eFuse region of the substrate;
forming a first gate oxide layer on a surface of the eFuse trench;
forming a dummy buried word line on the first gate oxide layer;
forming a plurality of doped regions respectively in the substrate on opposite sides outside the eFuse trench, wherein the plurality of doped regions are in contact with the first gate oxide layer; and
forming an eFuse gate electrode on the dummy buried word line and in contact with the first gate oxide layer, wherein the dummy buried word line is electrically isolated from the eFuse gate electrode.

### Claim 11 (depends on 10)

The method for manufacturing the memory device as claimed in claim 10, wherein forming the eFuse structure further comprises:
forming an insulating filling layer on the dummy buried word line after the dummy buried word line is formed, thereby electrically isolating the dummy buried word line from the eFuse gate electrode,
wherein a portion of the eFuse gate electrode that contacts the first gate oxide layer has a first thickness D1, and each of the plurality of doped regions has a depth D2 greater than the first thickness D1.

### Claim 12 (depends on 11)

The method for manufacturing the memory device as claimed in claim 11, further comprising:
forming a second gate oxide layer on the substrate and the insulating filling layer after the insulating filling layer is formed and before the eFuse gate electrode is formed,
patterning the second gate oxide layer to form an opening in the second gate oxide layer;
partially removing the insulating filling layer to form a receiving space in the eFuse trench, wherein the receiving space is in communication with the opening of the second gate oxide layer, and a removed portion of the insulating filling layer has the first thickness,
wherein forming the eFuse gate electrode on the dummy buried word line comprises forming the eFuse gate electrode in the receiving space, and
wherein the opening exposes the eFuse gate electrode, and a width of the opening is less than a bottom width of the eFuse gate electrode.

### Claim 13 (depends on 10)

The method for manufacturing the memory device as claimed in claim 10, further comprising:
forming a metal silicide layer on the eFuse gate electrode;
forming a metal layer on the metal silicide layer;
forming a capping layer on the metal layer;
patterning the metal silicide layer, the metal layer and the capping layer;
forming an insulating layer on the substrate, and making the insulating layer and the capping layer coplanar;
performing an etching process to form an opening in the capping layer, wherein the opening exposes the metal layer; and
forming a conductive layer in the opening, wherein a width of the conductive layer is less than or equal to a width of the metal layer,
wherein the metal silicide layer, the metal layer and the conductive layer form an eFuse contact structure.

### Claim 14 (depends on 10)

The method for manufacturing the memory device as claimed in claim 10, further comprising:
forming a word line trench in the array region of the substrate, wherein the word line trench and the eFuse trench are formed simultaneously; and
forming a buried word line in the word line trench, wherein the buried word line and the dummy buried word line are formed simultaneously.

### Claim 15 (depends on 14)

The method for manufacturing the memory device as claimed in claim 14, wherein the word line trench has a first width W1, the eFuse trench has a second width W2, and a ratio of the second width W2 to the first width W1 (W2/W1) is in a range of 2.0 to 5.0.

### Claim 16 (depends on 13)

The method for manufacturing the memory device as claimed in claim 13, further comprising:
forming a gate structure in a peripheral region of the substrate; and
forming a gate contact structure on the gate structure, wherein the gate contact structure and the eFuse contact structure are formed simultaneously.