# US 12,193,223 B2 · Memory device with improved anti-fuse read current > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,193,223 B2 - Document ID: US12193223B2 - Status: Granted - Kind: B2 - Application number: 18/447,638 - Filed: 2023-08-10 - Published: 2023-11-30 - Granted: 2025-01-07 - Earliest claimed: 2020-06-04 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Meng-Sheng Chang; Chia-En Huang; Yao-Jen Yang; Yih Wang - Web page: https://patentgrep.com/patent/US12193223B2 ## CPC - H10B 20/20: Programmable ROM [PROM] devices comprising field-effect components (H10B20/10 takes precedence) - H10W 20/491: {Antifuses, i.e. interconnections changeable from non-conductive to conductive} - G06F 30/392: Floor-planning or layout, e.g. partitioning or placement - G11C 17/16: using electrically-fusible links - H10B 20/25: One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links - H10W 20/43: Layouts of interconnections - H10B: ELECTRONIC MEMORY DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory device includes a first programming gate-strip for a first anti-fuse structure and a second programming gate-strip for a second anti-fuse structure. In the memory device, a terminal conductor overlies a terminal region between the channel regions of a first transistor and a second transistor. The memory device also includes a group of first programming conducting and a group of second programming conducting lines. The first programming conducting lines are conductively connected to the first programming gate-strip through a first group of one or more gate via-connectors. The second programming conducting lines are conductively connected to the second programming gate-strip through a second group of one or more gate via-connectors. ## Claims ### Claim 1 A memory device comprising: a first programming gate-strip and a second programming gate-strip both extending in a second direction perpendicular to a first direction; a first anti-fuse structure having a first dielectric layer overlying a first semiconductor region in an active zone at an intersection of the first programming gate-strip and the active zone extending in the first direction; a first transistor having a first channel region in the active zone; a second anti-fuse structure having a second dielectric layer overlying a second semiconductor region in the active zone at an intersection of the second programming gate-strip and the active zone; a second transistor having a second channel region in the active zone; a terminal conductor overlying a terminal region in the active zone between the first channel region of the first transistor and the second channel region of the second transistor; a group of first programming conducting lines, extending in the first direction, conductively connected to the first programming gate-strip through a first group of one or more gate via-connectors; and a group of second programming conducting lines, extending in the first direction, conductively connected to the second programming gate-strip through a second group of one or more gate via-connectors. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the first channel region is between the first semiconductor region and the terminal region, and the second channel region is between the second semiconductor region and the terminal region. ### Claim 3 (depends on 1) The memory device of claim 1, comprising: a first word programming line, extending in the second direction, conductively connected to the group of first programming conducting lines; and a second word programming line, extending in the second direction, conductively connected to the group of second programming conducting lines. ### Claim 4 (depends on 1) The memory device of claim 1, comprising: a bit connector conductively connected to the terminal conductor through one or more terminal via-connectors. ### Claim 5 (depends on 4) The memory device of claim 4, comprising: a bit conducting line, extending in the first direction, conductively connected to the bit connector. ### Claim 6 (depends on 1) The memory device of claim 1, comprising: a first read gate-strip and a second read gate-strip, both extending in the second direction, positioned between the first programming gate-strip and the second programming gate-strip. ### Claim 7 (depends on 6) The memory device of claim 6, further comprising: a first read conducting line, extending in the first direction, conductively connected to the first read gate-strip; and a second read conducting line, extending in the first direction, conductively connected to the second read gate-strip. ### Claim 8 (depends on 7) The memory device of claim 7, further comprising: a first word read line, extending in the second direction, conductively connected to the first read conducting line; and a second word read line, extending in the second direction, conductively connected to the second read conducting line. ### Claim 9 (depends on 8) The memory device of claim 8, wherein the first read gate-strip and the second read gate-strip are parallelly positioned between the first word read line and the second word read line. ### Claim 10 A memory device comprising: a first programming gate-strip and a second programming gate-strip both extending in a second direction perpendicular to a first direction; a first read gate-strip and a second read gate-strip, both extending in the second direction, positioned between the first programming gate-strip and the second programming gate-strip; a first anti-fuse structure having a first dielectric layer overlying a first semiconductor region in an active zone at an intersection of the first programming gate-strip and the active zone extending in the first direction; a first transistor having a first channel region in the active zone at an intersection of the first read gate-strip and the active zone; a second anti-fuse structure having a second dielectric layer overlying a second semiconductor region in the active zone at an intersection of the second programming gate-strip and the active zone; a second transistor having a second channel region in the active zone at an intersection of the second read gate-strip and the active zone; a terminal conductor overlying a terminal region in the active zone between the first channel region of the first transistor and the second channel region of the second transistor; a group of first programming conducting lines, extending in the first direction, conductively connected to the first programming gate-strip through a first group of one or more gate via-connectors; a group of second programming conducting lines, extending in the first direction, conductively connected to the second programming gate-strip through a second group of one or more gate via-connectors; and a bit connector conductively connected to the terminal conductor through one or more terminal via-connectors. ### Claim 11 (depends on 10) The memory device of claim 10, comprising: a first word programming line, extending in the second direction, conductively connected to the group of first programming conducting lines; and a second word programming line, extending in the second direction, conductively connected to the group of second programming conducting lines. ### Claim 12 (depends on 10) The memory device of claim 10, comprising: a bit conducting line, extending in the first direction, conductively connected to the bit connector. ### Claim 13 (depends on 10) The memory device of claim 10, comprising: a first read conducting line, extending in the first direction, conductively connected to the first read gate-strip; and a second read conducting line, extending in the first direction, conductively connected to the second read gate-strip. ### Claim 14 (depends on 13) The memory device of claim 13, further comprising: a first word read line, extending in the second direction, conductively connected to the first read conducting line; and a second word read line, extending in the second direction, conductively connected to the second read conducting line. ### Claim 15 (depends on 14) The memory device of claim 14, wherein the first read gate-strip and the second read gate-strip are parallelly positioned between the first word read line and the second word read line. ### Claim 16 A memory device comprising: a first programming gate-strip and a second programming gate-strip both extending in a second direction perpendicular to a first direction; a first read gate-strip and a second read gate-strip, both extending in the second direction, positioned between the first programming gate-strip and the second programming gate-strip; a first anti-fuse structure having a first dielectric layer overlying a first semiconductor region in an active zone at an intersection of the first programming gate-strip and the active zone extending in the first direction; a first transistor having a first channel region in the active zone at an intersection of the first read gate-strip and the active zone; a second anti-fuse structure having a second dielectric layer overlying a second semiconductor region in the active zone at an intersection of the second programming gate-strip and the active zone; a second transistor having a second channel region in the active zone at an intersection of the second read gate-strip and the active zone; a terminal conductor overlying a terminal region in the active zone between the first channel region of the first transistor and the second channel region of the second transistor; a group of first programming conducting lines, extending in the first direction, conductively connected to the first programming gate-strip through a first group of one or more gate via-connectors; a group of second programming conducting lines, extending in the first direction, conductively connected to the second programming gate-strip through a second group of one or more gate via-connectors; a first word programming line, extending in the second direction, conductively connected to the group of first programming conducting lines; and a second word programming line, extending in the second direction, conductively connected to the group of second programming conducting lines. ### Claim 17 (depends on 16) The memory device of claim 16, comprising: a bit connector conductively connected to the terminal conductor through one or more terminal via-connectors. ### Claim 18 (depends on 17) The memory device of claim 17, further comprising: a bit conducting line, extending in the first direction, conductively connected to the bit connector. ### Claim 19 (depends on 16) The memory device of claim 16, comprising: a first read conducting line, extending in the first direction, conductively connected to the first read gate-strip; and a second read conducting line, extending in the first direction, conductively connected to the second read gate-strip. ### Claim 20 (depends on 19) The memory device of claim 19, further comprising: a first word read line, extending in the second direction, conductively connected to the first read conducting line; and a second word read line, extending in the second direction, conductively connected to the second read conducting line. ### Claim 21 (depends on 20) The memory device of claim 20, wherein the first read gate-strip and the second read gate-strip are parallelly positioned between the first word read line and the second word read line.