# US 12,193,219 B2 · Apparatuses of controlling cross-layer reactions in semiconductor device

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- Number: US 12,193,219 B2
- Document ID: US12193219B2
- Status: Granted
- Kind: B2
- Application number: 17/688,743
- Filed: 2022-03-07
- Published: 2023-06-29
- Granted: 2025-01-07
- Earliest claimed: 2021-12-28
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Akie Shimamura; Kenichi Kusumoto
- Web page: https://patentgrep.com/patent/US12193219B2

## CPC

- H10B 12/482: {Bit lines}
- H10B 12/31: {having a storage electrode stacked over the transistor}
- H10B 12/315: {with the capacitor higher than a bit line}
- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10B 12/488: {Word lines}
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Apparatuses and methods for fabricating multilayer structures are described. An example method includes: forming a conductive base layer including silicon; forming a first conductive layer including first conductive material above the conductive base layer; forming a conductive barrier layer above the conductive layer; performing thermal loading to form a second conductive layer including silicide of the first conductive material between the conductive base layer and the conductive barrier layer; and forming a third conductive layer above the conductive barrier layer.

## Claims

### Claim 1

An apparatus, comprising:
a conductive base layer including silicon;
a first conductive layer including silicide of a conductive material above the conductive base layer;
a conductive barrier layer above the first conductive layer; and
a second conductive layer above the conductive barrier layer,
wherein the conductive barrier layer has a first thickness that is greater than a thickness of a first precursor conductive layer configured to form at least a lower portion of the conductive barrier layer and that is greater than a thickness of a second precursor conductive layer configured to form at least an upper portion of the conductive barrier layer,
wherein the second conductive layer has a second thickness that is greater than a thickness of a third precursor conductive layer configured to form at least a lower portion of the second conductive layer and that is greater than a thickness of a fourth precursor conductive layer configured to form at least an upper portion of the second conductive layer, and
wherein the second conductive layer includes ruthenium, the third precursor conductive layer includes ruthenium nitride, and the fourth precursor conductive layer includes ruthenium.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the first conductive layer is formed by forming a third conductive layer of the conductive material between forming the conductive base layer and forming the conductive barrier layer prior to the thermal loading.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the thermal loading is performed at a temperature within a range from 600° C. to 900° C.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the second conductive layer includes ruthenium.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the conductive barrier layer comprises:
the lower portion formed prior to the thermal loading; and
the upper portion formed after the thermal loading.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein the thermal loading is first thermal loading performed at a first temperature;
wherein the second conductive layer includes a lower portion and an upper portion;
wherein the upper portion of the conductive barrier layer and the lower portion of the second conductive layer are formed responsive to second thermal loading performed at a second temperature higher than the first temperature.

### Claim 7 (depends on 5)

The apparatus of claim 5, wherein the conductive barrier layer has the first thickness of 20-70 Å.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein
the conductive barrier layer includes titanium nitride,
the first precursor conductive layer includes titanium nitride, and
the second precursor conductive layer includes titanium.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein the first conductive layer is formed by thermal loading prior to forming the second conductive layer.

### Claim 10

An apparatus, comprising:
a memory cell array region including:
a substrate;
an isolation layer above the substrate;
one or more word lines embedded between the substrate and the isolation layer; and
a bit line on the isolation layer, including:
a conductive base layer including silicon on the isolation layer;
a first conductive layer including silicide of conductive material above the conductive base layer;
a conductive barrier layer above the first conductive layer; and
a second conductive layer as an electrode above the conductive barrier layer,
wherein the conductive barrier layer has a first thickness that is greater than a thickness of a first precursor conductive layer configured to form at least a lower portion of the conductive barrier layer and that is greater than a thickness of a second precursor conductive layer configured to form at least an upper portion of the conductive barrier layer,
wherein the second conductive layer has a second thickness that is greater than a thickness of a third precursor conductive layer configured to form at least a lower portion of the second conductive layer and that is greater than a thickness of a fourth precursor conductive layer configured to form at least an upper portion of the second conductive layer, and
wherein the second conductive layer includes ruthenium, the third precursor conductive layer includes ruthenium nitride, and the fourth precursor conductive layer includes ruthenium.

### Claim 11 (depends on 10)

The apparatus of claim 10, wherein the first conductive layer is formed by forming a third conductive layer of the conductive material between forming the conductive base layer and forming the conductive barrier layer prior to the thermal loading.

### Claim 12 (depends on 10)

The apparatus of claim 10, wherein the thermal loading is performed at a temperature within a range from 600° C. to 900° C.

### Claim 13 (depends on 10)

The apparatus of claim 10, wherein the second conductive layer includes ruthenium (Ru).

### Claim 14 (depends on 10)

The apparatus of claim 10, wherein the conductive barrier layer comprises:
the lower portion formed prior to the thermal loading; and
the upper portion formed after the thermal loading.

### Claim 15 (depends on 14)

The apparatus of claim 14, wherein the thermal loading is first thermal loading performed at a first temperature;
wherein the second conductive layer includes a lower portion and an upper portion;
wherein the upper portion of the conductive barrier layer and the lower portion of the second conductive layer are formed as reaction to second thermal loading performed at a second temperature higher than the first temperature.

### Claim 16 (depends on 14)

The apparatus of claim 14, wherein the conductive barrier layer has the first thickness of 20-70 Å.

### Claim 17 (depends on 10)

The apparatus of claim 10, wherein
the conductive barrier layer includes titanium nitride,
the first precursor conductive layer includes titanium nitride, and
the second precursor conductive layer includes titanium.

### Claim 18 (depends on 10)

The apparatus of claim 10, wherein the first conductive layer is formed by thermal loading prior to forming the second conductive layer.