# US 12,193,216 B2 · Semiconductor device having buried gate structure and method for fabricating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,193,216 B2 - Document ID: US12193216B2 - Status: Granted - Kind: B2 - Application number: 17/719,939 - Filed: 2022-04-13 - Published: 2023-03-30 - Granted: 2025-01-07 - Earliest claimed: 2021-09-29 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Yoon Jae Nam - Web page: https://patentgrep.com/patent/US12193216B2 ## CPC - H10B 12/34: {the transistor being at least partially in a trench in the substrate} - H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)} - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A semiconductor device includes a substrate including an active region defined by an isolation layer; a buried gate structure provided in a trench formed in the substrate; and a first doped region and a second doped region formed in the active region and separated by the trench, wherein the buried gate structure includes a gate dielectric layer conformally covering the trench; and a gate electrode including a first portion partially filling the trench on the gate dielectric layer and a second portion formed on the first portion, wherein the second portion includes a material included in the first portion and dopants including phosphorous (P), germanium (Ge), or a combination thereof, and wherein the first portion does not laterally overlap with the doped region and the second doped region, and all or a part of the second portion laterally overlaps with the first doped region and the second doped region. ## Claims ### Claim 1 A semiconductor device, comprising: a substrate including an active region defined by an isolation layer; a buried gate structure provided in a trench formed in the substrate; and a first doped region and a second doped region formed in the active region and separated by the trench, wherein the buried gate structure comprises: a gate dielectric layer conformally covering the trench; and a gate electrode including a first portion partially filling the trench on the gate dielectric layer and a second portion formed on the first portion, wherein the second portion comprises a material included in the first portion and dopants including phosphorous (P), germanium (Ge), or a combination thereof, wherein the first portion does not laterally overlap with the first doped region and the second doped region, and all or a part of the second portion laterally overlaps with the first doped region and the second doped region, and wherein sidewalls of the first and the second portions are aligned with each other, and the first portion has a height greater than that of the second portion. ### Claim 2 (depends on 1) The device of claim 1, wherein the first doped region and the second doped region have dopants including phosphorous (P), arsenic (As), or a combination thereof. ### Claim 3 (depends on 1) The device of claim 1, wherein the first doped region and the second doped region have the same dopant as each other. ### Claim 4 (depends on 1) The device of claim 1, wherein the first doped region and the second doped region have different dopants from each other. ### Claim 5 (depends on 1) The device of claim 1, wherein the first and the second portions have metal, metal nitride, metal silicide, or a combination thereof. ### Claim 6 (depends on 1) The device of claim 1, wherein the second portion has a work function lower than that of the first portion. ### Claim 7 A method for fabricating a semiconductor device comprising: forming a trench in a substrate including an active region defined by an isolation layer; forming a gate dielectric layer covering the trench; forming an initial gate electrode partially filling the trench on the gate dielectric layer; forming a gate electrode including a first portion and a second portion; and forming a first doped region and a second doped region on both sides of the trench, wherein the second portion differs from the first portion in that only the second portion includes at least one dopant, and wherein sidewalls of the first and the second portions are aligned with each other, and the first portion has a height greater than that of the second portion. ### Claim 8 (depends on 7) The method of claim 7, wherein the second portion of the gate electrode is formed by performing a first ion implantation process using at least one dopant selected from a group including phosphorous (P), and germanium (Ge). ### Claim 9 (depends on 8) The method of claim 8, wherein the first ion implantation process includes perpendicular ion implantation of the at least one dopant into the second portion of the gate electrode. ### Claim 10 (depends on 8) The method of claim 8, wherein the forming of the first and second doped regions includes a second ion implantation process performed by using at least one dopant selected from a group including phosphorous (P), and arsenic (As). ### Claim 11 (depends on 10) The method of claim 10, wherein the second ion implantation process includes a tilted ion implantation process. ### Claim 12 (depends on 11) The method of claim 11, wherein a tilt angle of the second ion implantation process is adjusted so that the first doped region and the second doped region do not laterally overlap with the first portion and overlap only with all or a part of the second portion. ### Claim 13 (depends on 10) The method of claim 10, wherein the first and the second ion implantation processes are simultaneously performed. ### Claim 14 (depends on 10) The method of claim 10, wherein the second ion implantation process is performed after the first ion implantation process. ### Claim 15 (depends on 10) The method of claim 10, wherein the first and the second ion implantation processes are performed by using the same at least one dopant. ### Claim 16 (depends on 10) The method of claim 10, wherein the first and the second ion implantation processes are performed by using a different at least one dopant from each other. ### Claim 17 (depends on 7) The method of claim 7, wherein a lower surface of the second portion is positioned at the same level as lower surfaces of the first and the second doped regions. ### Claim 18 (depends on 7) The method of claim 7, wherein an upper surface of the second portion is positioned at a level higher than lower surfaces of the first and the second doped regions, and a lower surface of the second portion is positioned as a level lower than lower surfaces of the first and the second doped regions. ### Claim 19 (depends on 7) The method of claim 7, wherein the initial gate electrode is formed of a metal, metal nitride, metal silicide, or a combination thereof, and the first portion includes a material included in the initial gate electrode and the second portion includes the material included in the initial gate electrode and dopants for modulating a work function.