# US 12,193,211 B2 · Method of manufacturing semiconductor device with word lines

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- Number: US 12,193,211 B2
- Document ID: US12193211B2
- Status: Granted
- Kind: B2
- Application number: 17/831,593
- Filed: 2022-06-03
- Published: 2023-12-07
- Granted: 2025-01-07
- Earliest claimed: 2022-06-03
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Ying-Cheng Chuang
- Web page: https://patentgrep.com/patent/US12193211B2

## CPC

- H10B 12/05: {Making the transistor}
- H10B 12/036: {the capacitor extending under the transistor}
- H10B 12/33: {the capacitor extending under the transistor}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/6728: {Vertical TFTs}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of manufacturing a semiconductor device is provided. The method includes: providing a substrate; forming a metallization layer on the substrate; forming an upper dielectric layer over the metallization layer; forming a first sacrificial layer and a second sacrificial layer, each of which penetrates the upper dielectric layer and the metallization layer; removing the upper dielectric layer; forming a width controlling structure between the first sacrificial layer and the second sacrificial layer, wherein the width controlling structure defines a recess exposing the metallization layer; forming a protective layer within the recess of the width controlling structure; removing the width controlling structure to expose a portion of the metallization layer; and patterning the metallization layer to form a word line between the first sacrificial layer and the second sacrificial layer.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, comprising:
providing a substrate comprising a first capacitor structure and a second capacitor structure therein;
forming a metallization layer on the substrate;
forming an upper dielectric layer over the metallization layer;
forming a first sacrificial layer and a second sacrificial layer, each of which penetrates the upper dielectric layer and the metallization layer, wherein the first sacrificial layer vertically overlaps the first capacitor structure and the second sacrificial layer vertically overlaps the second capacitor structure;
removing the upper dielectric layer;
forming a width controlling structure between the first sacrificial layer and the second sacrificial layer, wherein the width controlling structure defines a recess exposing the metallization layer;
forming a protective layer within the recess of the width controlling structure;
removing the width controlling structure to expose a portion of the metallization layer; and
patterning the metallization layer to form a word line between the first sacrificial layer and the second sacrificial layer.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming a first spacer on the first sacrificial layer and a second spacer on the second sacrificial layer, wherein the width controlling structure is between the first spacer and the second spacer.

### Claim 3 (depends on 2)

The method of claim 2, wherein forming the width controlling structure comprises:
forming a width controlling layer to cover the first sacrificial layer, the first spacer, the second sacrificial layer, the second spacer, and the metallization layer; and
removing a portion of the width controlling layer to form the width controlling structure.

### Claim 4 (depends on 3)

The method of claim 3, wherein the width controlling structure is free from vertically overlapping the first capacitor structure.

### Claim 5 (depends on 3)

The method of claim 3, wherein the width controlling structure is spaced apart from the first sacrificial layer via the first spacer.

### Claim 6 (depends on 3)

The method of claim 3, wherein a material of the first spacer is different from a material of the width controlling structure.

### Claim 7 (depends on 1)

The method of claim 1, wherein the width controlling structure is configured to determine a width of the word line.

### Claim 8 (depends on 1)

The method of claim 1, further comprising:
removing the first sacrificial layer and the second sacrificial layer to form a first hole and a second hole; and
forming a first channel layer within the first hole and a second channel layer within the second hole.

### Claim 9 (depends on 1)

The method of claim 1, wherein patterning the metallization layer comprises:
removing a portion of the metallization layer exposed by the first spacer, the second spacer, and the protective layer.

### Claim 10 (depends on 1)

The method of claim 1, further comprising:
forming a lower dielectric layer on the substrate, wherein the lower dielectric layer is disposed between the metallization layer and the substrate,
wherein a portion of the lower dielectric layer exposed by the first spacer, the second spacer, and the protective layer is removed.