# US 12,192,951 B2 · Synchronization of receiver and transmitter local oscillators for ranging applications > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,192,951 B2 - Document ID: US12192951B2 - Status: Granted - Kind: B2 - Application number: 18/618,458 - Filed: 2024-03-27 - Published: 2024-07-18 - Granted: 2025-01-07 - Earliest claimed: 2021-12-14 - Assignees: Silicon Laboratories Inc. - Applicants: Silicon Laboratories Inc. - Inventors: Rangakrishnan Srinivasan; John Khoury - Web page: https://patentgrep.com/patent/US12192951B2 ## CPC - H04W 64/00: Locating users or terminals {or network equipment} for network management purposes, e.g. mobility management - G06F 1/04: Generating or distributing clock signals or signals derived directly therefrom - H03L 7/18: using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) - H03L 7/23: with pulse counters or frequency dividers - H04L 7/0037: {Delay of clock signal} - H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop - H04L 7/041: {using special codes as synchronising signal} - H04W: WIRELESS COMMUNICATION NETWORKS (broadcast communication H04H; communication systems using wireless links for non-selective communication, e.g. wireless extensions H04M1/72) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract A system and method for accurately determining a distance between two network devices using a Channel Sounding application is disclosed. The network devices each guarantee a fixed phase relationship between the transmit circuit and the receive circuit. In one embodiment, this is achieved by disposing the divider outside the phase locked loop and using the output of the divider to create the clocks for both the transmit circuit and receive circuit. In another embodiment, one or more dividers are disposed outside the phase locked loop, each having a reset, such that they can be initialized to a predetermined state. Further, by utilizing a divider with a reset, the quadrature signal generator is guaranteed to output clocks for the transmit circuit and the receive circuit that have a constant phase relationship. ## Claims ### Claim 1 A method of performing a distance measurement between a first network device and a second network device, comprising: transmitting a first packet from the first network device to the second network device, using a first frequency; replying to the first packet by transmitting a second packet from the second network device to the first network device using the first frequency; transmitting a third packet from the first network device to the second network device using a second frequency, different from the first frequency; replying to the third packet by transmitting a fourth packet from the second network device to the first network device using the second frequency; and calculating a distance based on a phase received by the first network device and the second network device for each packet, the first frequency and the second frequency, wherein the first network device and the second network device each comprise a clock generation circuit having a phase locked loop and one divider disposed outside the phase locked loop to generate a receive clock and a transmit clock, such that a phase difference between the transmit clock and the receive clock of each network device is constant. ### Claim 2 (depends on 1) The method of claim 1, wherein the clock generation circuit comprises: a signal source to provide a REFCLK signal; the phase locked loop, comprising: a detector to determine a difference between the REFCLK signal and a feedback signal and provide an output based on the difference; a loop filter to filter the output to create a filtered output; an oscillator to generate a clock signal with a frequency related to the filtered output; a buffer to buffer the clock signal; and a multi-modulus divider in communication with an output of the buffer, to divide the output of the oscillator and supply the feedback signal to the detector; and the one divider in communication with the output of the buffer, to divide the clock signal by a quantity. ### Claim 3 (depends on 2) The method of claim 2, wherein the one divider comprises a reset signal so as to be initialized to a known state. ### Claim 4 (depends on 2) The method of claim 2, wherein the detector comprises a phase/frequency detector and charge pump and the oscillator comprises a voltage-controlled oscillator and the output from the phase/frequency detector and charge pump and the loop filter is a voltage. ### Claim 5 (depends on 2) The method of claim 2, wherein the detector comprises a time to digital converter, the output from the loop filter comprises a digital word and the oscillator comprises a digital-controlled oscillator. ### Claim 6 (depends on 1) The method of claim 1, wherein the clock generation circuit further comprises a quadrature signal generator in communication with an output of the one divider to generate the receive clock and the transmit clock. ### Claim 7 (depends on 6) The method of claim 6, wherein the quadrature signal generator outputs a transmit clock and a receive clock, such that the phase difference between the transmit clock and the receive clock is constant. ### Claim 8 (depends on 7) The method of claim 7, wherein the quadrature signal generator comprises a shift register. ### Claim 9 (depends on 8) The method of claim 8, wherein the quadrature signal generator comprises combinational logic, wherein the shift register and the combinational logic are used to generate the receive clock and the transmit clock. ### Claim 10 (depends on 9) The method of claim 9, wherein the receive clock output by the quadrature signal generator has a duty cycle of 12.5%, 25% or 50%. ### Claim 11 (depends on 9) The method of claim 9, wherein the shift register is used to generate the transmit clock and wherein the transmit clock output by the quadrature signal generator has a duty cycle of 12.5%, 25% or 50%. ### Claim 12 A method of performing a distance measurement between a first network device and a second network device, comprising: transmitting a first packet from the first network device to the second network device, using a first frequency; replying to the first packet by transmitting a second packet from the second network device to the first network device using the first frequency; transmitting a third packet from the first network device to the second network device using a second frequency, different from the first frequency; replying to the third packet by transmitting a fourth packet from the second network device to the first network device using the second frequency; and calculating a distance based on a phase received by the first network device and the second network device for each packet, the first frequency and the second frequency, wherein the first network device and the second network device comprises a clock generation circuit having a phase locked loop and two dividers disposed outside the phase locked loop to generate a receive clock and a transmit clock, such that a phase difference between the transmit clock and the receive clock of each network device is constant. ### Claim 13 (depends on 12) The method of claim 12, wherein the clock generation circuit comprises: a signal source to provide a REFCLK signal; the phase locked loop, comprising: a detector to determine a difference between the REFCLK signal and a feedback signal and provide an output based on the difference; a loop filter to filter the output to create a filtered output; an oscillator to generate a clock signal with a frequency related to the filtered output; a buffer to buffer the clock signal; and a multi-modulus divider in communication with an output of the buffer, to divide the output of the oscillator and supply the feedback signal to the detector; and a first divider in communication with the output of the buffer, to divide the clock signal by a first quantity; and a second divider in communication with the output of the buffer, to divide the clock signal by a second quantity. ### Claim 14 (depends on 13) The method of claim 13, wherein the detector comprises a phase/frequency detector and charge pump and the oscillator comprises a voltage-controlled oscillator and the output from the phase/frequency detector and charge pump and the loop filter is a voltage. ### Claim 15 (depends on 13) The method of claim 13, wherein the detector comprises a time to digital converter, the output from the loop filter comprises a digital word and the oscillator comprises a digital-controlled oscillator. ### Claim 16 (depends on 13) The method of claim 13, wherein an output of the first divider is used as an input to a transmit quadrature signal generator that generates a transmit clock, and an output of the second divider is used as an input to a receive quadrature signal generator that generates a received clock, and the phase difference between the transmit clock and the receive clock is constant. ### Claim 17 (depends on 16) The method of claim 16, wherein the first divider and the second divider use a common reset signal so that each is initialized to a known state. ### Claim 18 (depends on 16) The method of claim 16, wherein the first divider uses a first reset signal and the second divider uses a second reset signal so that each is initialized to a known state. ### Claim 19 A method of performing a distance measurement between a first network device and a second network device, comprising: transmitting a first packet from the first network device to the second network device, using a first frequency; replying to the first packet by transmitting a second packet from the second network device to the first network device using the first frequency; transmitting a third packet from the first network device to the second network device using a second frequency, different from the first frequency; replying to the third packet by transmitting a fourth packet from the second network device to the first network device using the second frequency; and calculating a distance based on a phase received by the first network device and the second network device for each packet, the first frequency and the second frequency, wherein the first network device and the second network device comprises a clock generation circuit having two phase locked loops and two dividers disposed outside a respective phase locked loop to generate a receive clock and a transmit clock, such that a phase difference between the transmit clock and the receive clock of each network device is constant. ### Claim 20 (depends on 19) The method of claim 19, wherein an output of a first divider is used as an input to a transmit quadrature signal generator that generates a transmit clock, and an output of a second divider is used as an input to a receive quadrature signal generator that generates a received clock, and the phase difference between the transmit clock and the receive clock is constant.