# US 12,192,664 B2 · Image sensor and operation method thereof

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,192,664 B2
- Document ID: US12192664B2
- Status: Granted
- Kind: B2
- Application number: 18/303,586
- Filed: 2023-04-20
- Published: 2023-11-16
- Granted: 2025-01-07
- Earliest claimed: 2022-05-13
- Assignees: Guangzhou Tyrafos Semiconductor Technologies Co., LTD
- Applicants: Guangzhou Tyrafos Semiconductor Technologies Co., LTD
- Inventors: Ping-Hung Yin; Jia-Shyang Wang; Yu-Hsiang Wang
- Web page: https://patentgrep.com/patent/US12192664B2

## CPC

- H04N 25/78: Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
- G06F 1/08: Clock generators with changeable or programmable clock frequency
- H03K 19/018521: {of complementary type, e.g. CMOS}
- H03L 7/099: concerning mainly the controlled oscillator of the loop
- H04N 25/60: Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N 25/627: Detection or reduction of inverted contrast or eclipsing effects
- H04N 25/63: applied to dark current
- H04N 25/709: Circuitry for control of the power supply
- H04N 25/77: Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
- H04N 25/772: comprising A/D, V/T, V/F, I/T or I/F converters
- H04N 25/778: comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
- H04N 25/779: Circuitry for scanning or addressing the pixel array
- H04N 25/7795: {Circuitry for generating timing or clock signals}
- H10F 39/026: {Wafer-level processing}
- H10F 39/8037: {the integrated elements comprising a transistor}
- H10F 39/811: {Interconnections}
- H10W 90/00: Package configurations
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An image sensor and an operating method thereof are provided. The image sensor includes a first pixel circuit, a first column readout circuit, and a second column readout circuit. The first pixel circuit includes a first pixel unit, a first transfer transistor, a first reset transistor, a first readout transistor, and a first capacitor. The first column readout circuit includes a first circuit node. The second column readout circuit includes a bias transistor. A first terminal of the first reset transistor and a first terminal of the first readout transistor are coupled to the first circuit node, and a second terminal of the first readout transistor is coupled to the bias transistor.

## Claims

### Claim 1

An image sensor, comprising:
a first pixel circuit, comprising:
a first pixel unit;
a first transfer transistor, wherein a first terminal of the first transfer transistor is coupled to a first floating diffusion node, and a second terminal of the first transfer transistor is coupled to the first pixel unit;
a first reset transistor, coupled to the first floating diffusion node;
a first readout transistor, wherein a control terminal of the first readout transistor is coupled to the first floating diffusion node; and
a first capacitor, coupled between a ramp signal and the floating diffusion node;
a first column readout circuit, comprising a first circuit node; and
a second column readout circuit, comprising a bias transistor,
wherein a first terminal of the first reset transistor and a first terminal of the first readout transistor are coupled to the first circuit node, and a second terminal of the first readout transistor is coupled to the bias transistor.

### Claim 2 (depends on 1)

The image sensor according to claim 1, wherein a first terminal of the readout transistor is coupled to the first circuit node, and the first terminal of the readout transistor is a drain terminal.

### Claim 3 (depends on 1)

The image sensor according to claim 1, wherein the ramp signal is an up-ramp signal or a down-ramp signal.

### Claim 4 (depends on 1)

The image sensor according to claim 1, wherein the transfer transistor, the reset transistor, the readout transistor, and the selection transistor are respectively N-type transistors.

### Claim 5 (depends on 1)

The image sensor according to claim 1, wherein the column readout circuit further comprises:
a first transistor, wherein a first terminal of the first transistor is coupled to a first operating voltage, and a second terminal of the first transistor is coupled to the first circuit node and a first output terminal; and
a second transistor, wherein a first terminal of the second transistor is coupled to the first circuit node and the first output terminal, and a second terminal of the second transistor is coupled to a second operating voltage.

### Claim 6 (depends on 5)

The image sensor according to claim 5, further comprising:
a second pixel circuit, comprising:
a second pixel unit;
a second transfer transistor, wherein a first terminal of the second transfer transistor is coupled to a second floating diffusion node, and a second terminal of the second transfer transistor is coupled to the second pixel unit;
a second reset transistor, coupled to the second floating diffusion node; and
a second readout transistor, wherein a control terminal of the second readout transistor is coupled to the second floating diffusion node,
wherein the first column readout circuit further comprises a second circuit node,
wherein a first terminal of the second reset transistor and a first terminal of the second readout transistor are coupled to the second circuit node, and a second terminal of the second readout transistor is coupled to the bias transistor.

### Claim 7 (depends on 6)

The image sensor according to claim 6, wherein the column readout circuit further comprises:
a third transistor, wherein a first terminal of the third transistor is coupled to the first operating voltage, and the second terminal of the first transistor is coupled to the second circuit node and a second output terminal; and
a fourth transistor, wherein a first terminal of the fourth transistor is coupled to the second circuit node and the second output terminal, and a second terminal of the fourth transistor is coupled to the second operating voltage.

### Claim 8 (depends on 7)

The image sensor according to claim 7, wherein a control terminal of the first transistor is coupled to a control terminal of the third transistor, and a control terminal of the second transistor and a control terminal of the fourth transistor are coupled to a pull-down control signal.

### Claim 9 (depends on 7)

The image sensor according to claim 7, wherein the first transistor and the third transistor are respectively P-type transistors, and the second transistor and the fourth transistor are respectively N-type transistors.

### Claim 10 (depends on 7)

The image sensor according to claim 7, wherein the column readout circuit further comprises:
a fifth transistor, wherein a first terminal of the fifth transistor is coupled to the second terminal of the first transistor; and
a sixth transistor, wherein a first terminal of the sixth transistor is coupled to a second terminal of the third transistor;
wherein a control terminal of the fifth transistor is coupled to a control terminal of the sixth transistor.

### Claim 11 (depends on 10)

The image sensor according to claim 10, wherein a second terminal of the fifth transistor is coupled to a first terminal of a seventh transistor, and a second terminal of the sixth transistor is coupled to a first terminal of an eighth transistor,
wherein a control terminal of the seventh transistor is coupled to the first terminal of the seventh transistor, and a control terminal of the eighth transistor is coupled to the first terminal of the eighth transistor.

### Claim 12 (depends on 11)

The image sensor according to claim 11, wherein the fifth transistor and the sixth transistor are respectively P-type transistors, and the seventh transistor and the eighth transistor are respectively N-type transistors.

### Claim 13 (depends on 11)

The image sensor according to claim 11, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor form an operational amplifier.

### Claim 14 (depends on 12)

The image sensor according to claim 12, further comprising a pixel array, wherein a first column of the pixel array comprises a plurality of first pixel circuits, and a second column of the pixel array comprises a plurality of second pixel circuits,
wherein the first pixel circuits and the second pixel circuits are coupled to the bias transistor, and the first pixel circuits and the second pixel circuits are coupled to the operational amplifier.

### Claim 15 (depends on 5)

The image sensor according to claim 5, wherein during a reset period, a control terminal of the first reset transistor receives a first reset signal, and a control terminal of the transfer transistor first receives a transfer signal to reset the first photodiode voltage, and then turns off the transfer signal, and a control terminal of the second transistor receives a pull-down control signal to pull down the voltage of the first floating diffusion node;
wherein during a readout period, the control terminal of the first reset transistor receives the first reset signal to pull up the voltage of the floating diffusion node, and then the control terminal of the transfer transistor receives a transfer signal, so that the first readout transistor is turned on according to the ramp signal and a charge accumulated by the first floating diffusion node and provided by the first pixel unit, and reads out the charge accumulated by the first floating diffusion node to generate a readout signal from the first circuit node;
wherein during a pull-down period, the control terminal of the first reset transistor receives the first reset signal, and the control terminal of the second transistor receives a pull-down control signal to pull down the voltage of the first floating diffusion node.

### Claim 16

An operation method of an image sensor, wherein the image sensor comprises a first pixel circuit, a first column readout circuit, and a second column readout circuit, the first pixel circuit comprises a first pixel unit, a first transfer transistor, a first reset transistor, a first readout transistor, and a first capacitor, the first column readout circuit comprises a first circuit node, wherein a first terminal of the first reset transistor and a first terminal of the first readout transistor are coupled to the first circuit node, and a second terminal of the first readout transistor is coupled to the bias transistor, wherein the operation method comprises:
receiving a first reset signal through a control terminal of the first reset transistor during a reset period, and receiving a transfer signal first through a control terminal of the transfer transistor to reset a voltage of a first floating diffusion node, and then receiving a pull-down control signal through a control terminal of a second transistor to pull down the voltage of the first floating diffusion node;
receiving a transfer signal through the control terminal of the transfer transistor during a readout period, so that the first readout transistor is turned on according to the ramp signal and a charge accumulated by the first floating diffusion node and provided by the first pixel unit, and reading out the charge accumulated by the first floating diffusion node to generate a readout signal from the first circuit node; and
receiving the first reset signal through the control terminal of the first reset transistor during a pull-down period, and receiving a pull-down control signal through a control terminal of the second transistor to pull down the voltage of the first floating diffusion node.