# US 12,192,464 B2 · Method and apparatus for multi-adapter execution of look ahead video encoding > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,192,464 B2 - Document ID: US12192464B2 - Status: Granted - Kind: B2 - Application number: 18/018,182 - Filed: 2020-08-27 - Published: 2023-08-24 - Granted: 2025-01-07 - Earliest claimed: 2020-08-27 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Vasily Aristarkhov - Web page: https://patentgrep.com/patent/US12192464B2 ## CPC - H04N 19/127: Prioritisation of hardware or computational resources - H04N 19/423: characterised by memory arrangements (H04N19/433 takes precedence) - H04N 19/436: using parallelised computational arrangements - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract A multi-adapter encoding process where the first adapter is used to execute a look-ahead encoding process while the second adapter is used to execute a main encoding process is provided. The look-ahead encode and main encode can be executed concurrently on the different adapters. Additionally, the first adapter can execute the look-ahead encoding process without feedback from the second adapter, or the main encoding process. ## Claims ### Claim 1 A computing apparatus, comprising: a processor; first graphics processing circuitry; second graphics processing circuitry; and a memory device storing instructions, which when executed by the processor configure the apparatus to: receive a video stream at the first graphics processing circuitry, the video stream comprising indications of a plurality of frames; decode a first set of the plurality of frames by the first graphics processing circuitry; analyze the first set of the plurality of frames by the first graphics processing circuitry, the first set comprising at least a first frame and a second frame of the plurality of frames; generate, responsive to analyzing the first set of the plurality of frames, first encoding parameters for the first frame of the plurality of frames; provide, to the second graphics processing circuitry, an indication of the first frame of the plurality of frames and an indication of the first encoding parameters; and encode, by the second graphics processing circuitry, the first frame based on the indication of the first one of the plurality of frames and the indication of the first encoding parameters. ### Claim 2 (depends on 1) The computing apparatus of claim 1, the first of the plurality of frames comprising the first one of the plurality of frames through an Nth one of the plurality of frames, the memory device storing further instructions, which when executed by the processor configure the apparatus to: analyze, by the first graphics processing circuitry, an Nth+1 frame of the plurality of frames; generate, responsive to analyzing the Nth+1 frame of the plurality of frames, second encoding parameters for the second frame of the plurality of frames; provide, to the second graphics processing circuitry, an indication of the second frame of the plurality of frames and an indication of the second encoding parameters; and encode, by the second graphics processing circuitry, the second frame based on the indication of the second frame of the plurality of frames and the indication of the second encoding parameters. ### Claim 3 (depends on 2) The computing apparatus of claim 2, the memory device storing further instructions, which when executed by the processor configure the apparatus to: analyze, by the first graphics processing circuitry, an Nth+2 frame of the plurality of frames; generate, responsive to analyzing the Nth+2 frame of the plurality of frames, third encoding parameters for the third frame of the plurality of frames; provide, to third graphics processing circuitry, an indication of the third frame of the plurality of frames and an indication of the third encoding parameters; and encode, by the third graphics processing circuitry, the third frame based on the indication of the third frame of the plurality of frames and the indication of the third encoding parameters. ### Claim 4 (depends on 1) The computing apparatus of claim 1, the memory device storing further instructions, which when executed by the processor configure the apparatus to receive at the first graphics processing circuitry an indication of a frame size of the encoded first frame. ### Claim 5 (depends on 1) The computing apparatus of claim 1, wherein the second graphics processing circuitry comprises a first graphics process unit (GPU) and a second GPU, the memory device storing further instructions, which when executed by the processor configure the apparatus to: encode, by the first GPU, a first slice of the first frame; and encode, by the second GPU, a second slice of the first frame. ### Claim 6 (depends on 1) The computing apparatus of claim 1, wherein the first graphics processing circuitry comprising a first graphics process unit (GPU) and the second circuitry comprising a second GPU. ### Claim 7 (depends on 6) The computing apparatus of claim 6, wherein the first graphics processing circuitry comprises an integrated GPU and the second graphics processing circuitry comprises a dedicated GPU. ### Claim 8 (depends on 6) The computing apparatus of claim 6, wherein the first GPU supports a first encoding codec and the second GPU supports a second encoding codec different from the first encoding codec. ### Claim 9 (depends on 6) The computing apparatus of claim 6, wherein the first GPU comprises less computing resources, less memory, or less computing resources and less memory than the second GPU. ### Claim 10 A method, comprising: receiving a video stream at first circuitry, the video stream comprising indications of a plurality of frames; decoding a first set of the plurality of frames by the first circuitry; analyzing the first set of the plurality of frames by the first circuitry, the first set comprising at least a first frame and a second frame of the plurality of frames; generating, responsive to analyzing the first set of the plurality of frames, first encoding parameters for the first frame of the plurality of frames; providing, to second circuitry different from the first circuitry, an indication of the first frame of the plurality of frames and an indication of the first encoding parameters; and encoding, by the second circuitry, the first frame based on the indication of the first one of the plurality of frames and the indication of the first encoding parameters. ### Claim 11 (depends on 10) The method of claim 10, the first of the plurality of frames comprising the first one of the plurality of frames through an Nth one of the plurality of frames, the method comprising: analyzing, by the first circuitry, an Nth+1 frame of the plurality of frames; generating, responsive to analyzing the Nth+1 frame of the plurality of frames, second encoding parameters for the second frame of the plurality of frames; providing, to the second circuitry, an indication of the second frame of the plurality of frames and an indication of the second encoding parameters; and encoding, by the second circuitry, the second frame based on the indication of the second frame of the plurality of frames and the indication of the second encoding parameters. ### Claim 12 (depends on 11) The method of claim 11, comprising: analyzing, by the first circuitry, an Nth+2 frame of the plurality of frames; generating, responsive to analyzing the Nth+2 frame of the plurality of frames, third encoding parameters for the third frame of the plurality of frames; providing, to third circuitry, an indication of the third frame of the plurality of frames and an indication of the third encoding parameters, the third circuitry different from the first circuitry and the second circuitry; and encoding, by the third circuitry, the third frame based on the indication of the third frame of the plurality of frames and the indication of the third encoding parameters. ### Claim 13 (depends on 10) The method of claim 10, comprising receiving at the first circuitry an indication of a frame size of the encoded first frame. ### Claim 14 A non-transitory computer-readable storage medium, the computer-readable storage medium including instructions that when executed by a computer, cause the computer to: receive a video stream at first circuitry, the video stream comprising indications of a plurality of frames; decode a first set of the plurality of frames by the first circuitry; analyze the first set of the plurality of frames by the first circuitry, the first set comprising at least a first frame and a second frame of the plurality of frames; generate, responsive to analyzing the first set of the plurality of frames, first encoding parameters for the first frame of the plurality of frames; provide, to second circuitry different from the first circuitry, an indication of the first frame of the plurality of frames and an indication of the first encoding parameters; and encode, by the second circuitry, the first frame based on the indication of the first one of the plurality of frames and the indication of the first encoding parameters. ### Claim 15 (depends on 14) The computer-readable storage medium of claim 14, the first of the plurality of frames comprising the first one of the plurality of frames through an Nth one of the plurality of frames, the instructions, when executed by the computer, cause the computer to: analyze, by the first circuitry, an Nth+1 frame of the plurality of frames; generate, responsive to analyzing the Nth+1 frame of the plurality of frames, second encoding parameters for the second frame of the plurality of frames; provide, to the second circuitry, an indication of the second frame of the plurality of frames and an indication of the second encoding parameters; and encode, by the second circuitry, the second frame based on the indication of the second frame of the plurality of frames and the indication of the second encoding parameters. ### Claim 16 (depends on 15) The computer-readable storage medium of claim 15, the instructions, when executed by the computer, cause the computer to: analyze, by the first circuitry, an Nth+2 frame of the plurality of frames; generate, responsive to analyzing the Nth+2 frame of the plurality of frames, third encoding parameters for the third frame of the plurality of frames; provide, to third circuitry, an indication of the third frame of the plurality of frames and an indication of the third encoding parameters, the third circuitry different from the first circuitry and the second circuitry; and encode, by the third circuitry, the third frame based on the indication of the third frame of the plurality of frames and the indication of the third encoding parameters. ### Claim 17 (depends on 14) The computer-readable storage medium of claim 14, wherein the second circuitry comprises a first graphics process unit (GPU) and a second GPU, the instructions, when executed by the computer, cause the computer to: encode, by the first GPU, a first slice of the first frame; and encode, by the second GPU, a second slice of the first frame.