# US 12,192,329 B2 · Multi-factor authentication for a memory system based on internal asymmetric keys > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,192,329 B2 - Document ID: US12192329B2 - Status: Granted - Kind: B2 - Application number: 17/663,124 - Filed: 2022-05-12 - Published: 2023-04-27 - Granted: 2025-01-07 - Earliest claimed: 2021-10-22 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Lance W. Dover - Web page: https://patentgrep.com/patent/US12192329B2 ## CPC - H04L 9/0825: {using asymmetric-key encryption or public key infrastructure [PKI], e.g. key signature or public key certificates} - H04L 9/0841: {involving Diffie-Hellman or related key agreement protocols} - H04L 9/085: {Secret sharing or secret splitting, e.g. threshold schemes} - H04L 9/3263: {involving certificates, e.g. public key certificate [PKC] or attribute certificate [AC]; Public key infrastructure [PKI] arrangements (network architectures or network communication protocols for supporting authentication of entities using certificates in a packet data network H04L63/0823)} - H04L 9/3278: {using physically unclonable functions [PUF]} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract Methods, systems, and devices for multi-factor authentication for memory systems based on internal asymmetric keys are described. In some examples, host systems and memory systems may be configured to implement techniques for the generation and distribution of asymmetric keys, certificates, or both, which may support evaluating the authenticity of interfacing systems (e.g., by signing and verifying exchanged signaling based on system identities) or protecting the integrity of exchanged signaling (e.g., by encrypting exchanged signaling), or both. Such techniques may include implementing asymmetric cryptographic security functionality directly in a memory system, including techniques where the memory system is configured to generate asymmetric key pairs, certificates, or both based on a combination of unique device secret and content stored at the memory system. ## Claims ### Claim 1 A memory system, comprising: one or more memory devices; and processing circuitry coupled with the one or more memory devices and configured to cause the memory system to: generate a key based at least in part on a unique device secret associated with the memory system and on content stored at the memory system; generate an asymmetric key pair comprising a private key based at least in part on the generated key and a public key based at least in part on the generated key; generate a certificate based at least in part on the generated asymmetric key pair; and transmit the generated certificate. ### Claim 2 (depends on 1) The memory system of claim 1, wherein the content stored at the memory system comprises boot code stored at the memory system. ### Claim 3 (depends on 1) The memory system of claim 1, wherein the processing circuitry is configured to cause the memory system to: derive the unique device secret based at least in part on accessing a physical unclonable function of the memory system. ### Claim 4 (depends on 1) The memory system of claim 1, wherein the processing circuitry is configured to cause the memory system to: receive content from a host system; and generate a second certificate for operation with the host system based at least in part on the generated private key and the content received from the host system. ### Claim 5 (depends on 4) The memory system of claim 4, wherein the content received from the host system comprises boot code received from the host system. ### Claim 6 (depends on 1) The memory system of claim 1, wherein the public key is generated based at least in part on the generated private key. ### Claim 7 (depends on 1) The memory system of claim 1, wherein the processing circuitry is configured to cause the memory system to: transmit the generated public key to a host system separate from transmitting the generated certificate. ### Claim 8 (depends on 1) The memory system of claim 1, wherein the processing circuitry is configured to cause the memory system to: generate a second key that is different than the generated key, the generated second key based at least in part on the unique device secret associated with the memory system and the content stored at the memory system; and transmit the generated second key. ### Claim 9 (depends on 1) The memory system of claim 1, wherein the memory system comprises a semiconductor chip that is operable for coupling with a host system and is configured for generating the asymmetric key pair and for generating the certificate for operation with the host system. ### Claim 10 (depends on 9) The memory system of claim 9, wherein the semiconductor chip comprises the one or more memory devices. ### Claim 11 (depends on 1) The memory system of claim 1, wherein the one or more memory devices stores boot code for execution by a host system, and wherein the processing circuitry is configured to cause the memory system to: generate a second certificate for operation with the host system based at least in part on the generated private key and the boot code for execution by the host system. ### Claim 12 A non-transitory computer-readable medium storing code comprising instructions which, when executed by processing circuitry of an electronic device, cause the electronic device to: generate, at a memory system, a key based at least in part on a unique device secret associated with the memory system and on content stored at the memory system; generate, at the memory system, an asymmetric key pair comprising a private key based at least in part on the generated key and a public key based at least in part on the generated key; generate, at the memory system, a certificate for operation with a host system based at least in part on the generated asymmetric key pair; and transmit, by the memory system, the generated certificate to the host system. ### Claim 13 (depends on 12) The non-transitory computer-readable medium of claim 12, wherein the content stored at the memory system comprises boot code stored at the memory system. ### Claim 14 (depends on 12) The non-transitory computer-readable medium of claim 12, further comprising instructions which, when executed by the processing circuitry, cause the electronic device to: derive the unique device secret based at least in part on accessing a physical unclonable function of the memory system. ### Claim 15 (depends on 12) The non-transitory computer-readable medium of claim 12, further comprising instructions which, when executed by the processing circuitry, cause the electronic device to: receive, at the memory system, content from the host system; and generate, at the memory system, a second certificate for operation with the host system based at least in part on the generated private key and the content received from the host system. ### Claim 16 (depends on 15) The non-transitory computer-readable medium of claim 15, wherein the content received from the host system comprises boot code received from the host system. ### Claim 17 (depends on 12) The non-transitory computer-readable medium of claim 12, wherein the public key is generated based at least in part on the generated private key. ### Claim 18 (depends on 12) The non-transitory computer-readable medium of claim 12, further comprising instructions which, when executed by the processing circuitry, cause the electronic device to: transmit, by the memory system, the generated public key to the host system separate from transmitting the generated certificate. ### Claim 19 (depends on 12) The non-transitory computer-readable medium of claim 12, further comprising instructions which, when executed by the processing circuitry, cause the electronic device to: generate, at the memory system, a second key that is different than the generated key, the generated second key based at least in part on the unique device secret associated with the memory system and the content stored at the memory system; and transmit, by the memory system, the generated second key. ### Claim 20 (depends on 12) The non-transitory computer-readable medium of claim 12, wherein the memory system comprises a semiconductor chip that is operable for coupling with the host system and is configured for generating the asymmetric key pair and for generating the certificate for the operation with the host system. ### Claim 21 A method, comprising: generating, at a memory system, a key based at least in part on a unique device secret associated with the memory system and on content stored at the memory system; generating, at the memory system, an asymmetric key pair comprising a private key based at least in part on the generated key and a public key based at least in part on the generated key; generating, at the memory system, a certificate for operation with a host system based at least in part on the generated asymmetric key pair; and transmitting, by the memory system, the generated certificate to the host system. ### Claim 22 (depends on 21) The method of claim 21, wherein the content stored at the memory system comprises boot code stored at the memory system. ### Claim 23 (depends on 21) The method of claim 21, further comprising: deriving the unique device secret based at least in part on accessing a physical unclonable function of the memory system. ### Claim 24 (depends on 21) The method of claim 21, further comprising: receiving, at the memory system, content from the host system; and generating, at the memory system, a second certificate for operation with the host system based at least in part on the generated private key and the content received from the host system. ### Claim 25 (depends on 21) The method of claim 21 wherein the public key is generated based at least in part on the generated private key.