# US 12,191,988 B2 · Data processing method, precoding method, and communication device

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- Number: US 12,191,988 B2
- Document ID: US12191988B2
- Status: Granted
- Kind: B2
- Application number: 18/422,563
- Filed: 2024-01-25
- Published: 2024-07-18
- Granted: 2025-01-07
- Earliest claimed: 2013-01-11
- Assignees: Sun Patent Trust
- Applicants: Sun Patent Trust
- Inventors: Yutaka Murakami; Tomohiro Kimura; Mikihiro Ouchi
- Web page: https://patentgrep.com/patent/US12191988B2

## CPC

- H04L 1/0004: {applied to control information}
- H03M 13/255: {with Low Density Parity Check [LDPC] codes}
- H04B 7/0413: MIMO systems
- H04L 1/0003: {by switching between different modulation schemes}
- H04L 1/003: {Adaptive formatting arrangements particular to signalling, e.g. variable amount of bits}
- H04L 1/0057: {Block codes (H04L1/0061, H04L1/0064 take precedence)}
- H04L 1/0067: {Rate matching (H04L1/0013 and H04L1/08 take precedence)}
- H04L 1/0071: {Use of interleaving (interleaving per se H03M13/27)}
- H04L 1/08: by repeating transmission, e.g. Verdan system {(H04L1/1858 and H04L1/189 take precedence)}
- H04L 5/005: {of common pilots, i.e. pilots destined for multiple users or terminals}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H04B: TRANSMISSION

## Abstract

An encoder outputs a first bit sequence having N bits. A mapper generates a first complex signal s1 and a second complex signal s2 with use of bit sequence having X+Y bits included in an input second bit sequence, where X indicates the number of bits used to generate the first complex signal s1, and Y indicates the number of bits used to generate the second complex signal s2. A bit length adjuster is provided after the encoder, and performs bit length adjustment on the first bit sequence such that the second bit sequence has a bit length that is a multiple of X+Y, and outputs the first bit sequence after the bit length adjustment as the second bit sequence. As a result, a problem between a codeword length of a block code and the number of bits necessary to perform mapping by a set of modulation schemes is solved.

## Claims

### Claim 1

A transmission device comprising:
at least one processor configured to:
generate a first modulated signal and a second modulated signal by performing encoding and mapping on information to be transmitted,
perform first phase change on the first modulated signal and the second modulated signal to generate a first phase-changed signal and a second phase-changed signal, respectively, and
perform second phase change only on the first phase-changed signal to generate a first transmission signal; and
a transmitter configured to transmit the first transmission signal and the second phase-changed signal via a first antenna and a second antenna, respectively.

### Claim 2 (depends on 1)

The transmission device according to claim 1, wherein the at least one processor is further configured to:
perform precoding on the first phase-changed signal and the second phase-changed signal according to a precoding matrix F; and
perform the second phase change on the first phase-changed signal which has been subjected to the precoding.

### Claim 3 (depends on 2)

The transmission device according to claim 2, wherein the precoding matrix F is changed slot-by-slot.