# US 12,191,893 B2 · Seemingly monolithic interface between separate integrated circuit die

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- Number: US 12,191,893 B2
- Document ID: US12191893B2
- Status: Granted
- Kind: B2
- Application number: 17/385,556
- Filed: 2021-07-26
- Published: 2022-06-16
- Granted: 2025-01-07
- Earliest claimed: 2016-12-28
- Assignees: Altera Corporation
- Applicants: Intel Corporation
- Inventors: David W. Mendel; Jeffrey Erik Schulz; Keith Duwel; Huy Ngo; Jakob Raymond Jones
- Web page: https://patentgrep.com/patent/US12191893B2

## CPC

- H03M 9/00: Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00)
- G06F 1/12: Synchronisation of different clock signals {provided by a plurality of clock generators}
- G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)}
- H03K 19/17744: {for input/output signals}
- H10W 70/63: Vias, e.g. via plugs
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A seemingly monolithic interface between separate integrated circuit die may appear to be parallel or asynchronous from the perspective of the separate integrated circuit die. The signals of the seemingly monolithic interface, however, may actually be communicated between the separate die via serial and/or synchronous communication. In one method, a number of signals stored in a first parallel interface on a first integrated circuit die may be sampled. In some cases, at least one of the signals may be sampled more often than another one of the signals. A serial signal may be generated based on sampled signals. The serial signal may be transmitted to a corresponding second parallel interface on the second integrated circuit die.

## Claims

### Claim 1

An integrated circuit device comprising:
a sampling circuitry to sample a first portion of a plurality of signals more often than a second portion of the plurality of signals; and
a transmitter to generate a serial signal based on the plurality of signals and transmit the serial signal, wherein a frame of the serial signal comprises a first time slot comprising a flag bit indicating a state of a plurality of bits of the first time slot, a first plurality of time slots that comprise the first portion of the plurality of signals, and a second plurality of time slots that comprise the second portion of the plurality of signals.

### Claim 2 (depends on 1)

The integrated circuit device of claim 1, comprising a first die, wherein the first die comprises the sampling circuitry and the transmitter.

### Claim 3 (depends on 2)

The integrated circuit device of claim 2, wherein the first die comprises an interface to store the plurality of signals.

### Claim 4 (depends on 2)

The integrated circuit device of claim 2, wherein:
the first plurality of time slots of the frame comprises a first number of time slots;
the second plurality of time slots of the frame comprises a second number of time slots; and
the first number of time slots is greater than the second number of time slots.

### Claim 5 (depends on 2)

The integrated circuit device of claim 2, comprising a second die, wherein the second die comprises a receiver to receive the serial signal from the first die.

### Claim 6 (depends on 5)

The integrated circuit device of claim 5, wherein the second die comprises:
deserialization circuitry to obtain the plurality of signals based on the serial signal; and
a second interface to store the plurality of signals obtained by the deserialization circuitry.

### Claim 7 (depends on 5)

The integrated circuit device of claim 5, wherein the second die is to communicatively couple the first die to circuitry located external to the integrated circuit device.

### Claim 8 (depends on 7)

The integrated circuit device of claim 7, wherein the first die comprises a processor.

### Claim 9 (depends on 7)

The integrated circuit device of claim 7, comprising a substrate, wherein:
the first die and the second die are mounted on the substrate; and
the substrate comprises interconnect circuitry to communicatively couple the transmitter to the receiver.

### Claim 10 (depends on 1)

The integrated circuit device of claim 1, wherein the first time slot is positioned before the first plurality of time slots or the second plurality of time slots.

### Claim 11

A system comprising:
a substrate;
a first integrated circuit die mounted on the substrate, the first integrated circuit die comprising:
sampling circuitry to sample a first portion of a plurality of signals more often than a second portion of the plurality of signals; and
a transmitter to generate a serial signal based on the plurality of signals and transmit the serial signal, wherein a frame of the serial signal comprises a first time slot comprising a flag bit to indicate a state of a plurality of bits of the first time slot, a first plurality of time slots that comprise the first portion of the plurality of signals, and a second plurality of time slots that comprise the second portion of the plurality of signals, wherein the first plurality of time slots includes more time slots than the second plurality of time slots; and
a second integrated circuit die mounted on the substrate, the second integrated circuit die comprising a receiver to receive, via the substrate, the serial signal from the first integrated circuit die.

### Claim 12 (depends on 11)

The system of claim 11, wherein the sampling circuitry is to cause the plurality of signals to be sampled according to a first clock over a sampling window that includes a plurality of edges of the first clock, wherein the first portion of the plurality of signals is sampled at least in part by:
detecting a current state of a signal of the first portion of the plurality of signals a defined number of times at edges of the first clock;
latching the signal when the current state is the same for the defined number of times; and
outputting the latched signal into a sampling register.

### Claim 13 (depends on 11)

The system of claim 11, wherein:
the first integrated circuit die comprises a processor; and
the second integrated circuit die is to communicatively couple the processor to circuitry external to the system.

### Claim 14 (depends on 11)

The system of claim 11, wherein the sampling circuitry is to sample the first portion of the plurality of signals at least twice as often as the second portion of the plurality of signals.

### Claim 15 (depends on 11)

The system of claim 11, wherein the second integrated circuit die comprises:
deserialization circuitry to obtain the plurality of signals based on the serial signal; and
a second interface to store the plurality of signals obtained by the deserialization circuitry.

### Claim 16 (depends on 11)

The integrated circuit device of claim 11, wherein the first time slot is positioned before the first plurality of time slots or the second plurality of time slots.

### Claim 17

A system comprising:
a substrate; and
a first integrated circuit die mounted on the substrate, wherein the first integrated circuit die comprises:
sampling circuitry clocked to a clock, wherein the sampling circuitry is to:
receive a plurality of signals comprising a signal and a second signal;
sample the signal at a first sampling rate to produce a first plurality of sampled signals, wherein the signal is sampled over a sampling window that includes a plurality of edges of the clock, wherein the signal is sampled at least in part by:
detecting a current state of the signal a defined number of times at edges of the clock;
latching the signal when the current state is the same for the defined number of times; and
outputting the latched signal into a sampling register; and
sample the second signal of the plurality of signals at a second sampling rate to produce a second plurality of sampled signals, wherein the first sampling rate is a higher frequency than the second sampling rate;
a transmitter to generate a serial signal based on the plurality of signals transmit the serial signal, wherein a frame of the serial signal comprises:
a first plurality of time slots that comprises the first plurality of sampled signals; and
a second plurality of time slots that comprises the second plurality of sampled signals.

### Claim 18 (depends on 17)

The system of claim 17, comprising a second integrated circuit die mounted on the substrate, wherein the second integrated circuit die comprises a receiver to receive, via the substrate, the serial signal.

### Claim 19 (depends on 18)

The system of claim 18, wherein:
the first integrated circuit die comprises a processor; and
the second integrated circuit die is to communicatively couple the processor to circuitry external to the system.

### Claim 20 (depends on 18)

The system of claim 18, wherein the second integrated circuit die comprises:
deserialization circuitry to obtain the plurality of signals based on the serial signal; and
a second interface to store the plurality of signals obtained by the deserialization circuitry.