Analog-to-digital converter and analog-to-digital conversion method using the same

An analog-to-digital converter (ADC) comprising:

• a coarse ADC including a first capacitor array configured to determine N upper bits of a digital output signal corresponding to an analog input signal, a first comparator configured to receive a first asynchronous clock signal generated from a sampling clock signal to output a first comparison signal, and a first successive-approximation register (SAR) logic configured to generate a first comparison operation completion signal on a basis of the first comparison signal;
• and
• a fine ADC including a second capacitor array configured to determine N-n lower bits remaining after the digital output signal is generated,
• a second comparator configured to receive a second asynchronous clock signal generated by the first comparison operation completion signal to output a second comparison signal, and a second SAR logic configured to generate a second comparison operation completion signal on a basis of the second comparison signal.

An analog-to-digital conversion method comprising:

• generating, by a first asynchronous clock generator, a first asynchronous clock signal from a sampling clock signal;
• generating, by a first comparator, a first comparison signal on a basis of the first asynchronous clock signal;
• generating, by a first control logic, a first comparison operation completion signal on a basis of the first comparison signal;
• generating, by a second asynchronous clock generator, a second asynchronous clock signal from the first comparison operation completion signal;
• and
• generating, by a second comparator, a second comparison signal on a basis of the second asynchronous clock signal.