# US 12,191,879 B2 · Receiver

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- Number: US 12,191,879 B2
- Document ID: US12191879B2
- Status: Granted
- Kind: B2
- Application number: 18/379,840
- Filed: 2023-10-13
- Published: 2024-02-01
- Granted: 2025-01-07
- Earliest claimed: 2017-02-03
- Assignees: Novelda AS
- Applicants: Novelda AS
- Inventors: Jørgen Andreas Michaelsen; Nikolaj Andersen; Olav Tonnaer Liseth; Håkon André Hjortland
- Web page: https://patentgrep.com/patent/US12191879B2

## CPC

- H03M 1/1245: {Details of sampling arrangements or methods}
- H03M 1/502: {using tapped delay lines}
- G01S 7/2922: {by using a controlled threshold}
- G01S 7/2927: {by deriving and controlling a threshold value}
- G01S 13/0209: {Systems with very large relative bandwidth, i.e. larger than 10 %, e.g. baseband, pulse, carrier-free, ultrawideband}
- H03M 1/121: {Interleaved, i.e. using multiple converters or converter parts for one channel}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- G01S: RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES

## Abstract

A range profile digitization circuit for converting a repeating analog input signal into a time series of digital amplitude values, the converter comprising: a signal quantizer arranged to receive the analog input signal and a threshold input and arranged to output a binary value quantized output signal based on a comparison of the input signal with the threshold signal; a plurality of samplers each arranged to sample and hold its input signal upon receipt of a trigger signal; and for each sampler: a plurality of decoders and a demultiplexer arranged to receive an output from the sampler and pass it to a selected one of said decoders based on a selector input. With a plurality of decoders associated with each of the samplers, each sampler can be re-used during the building up of the range profile.

## Claims

### Claim 1

A range profile digitization circuit for converting a repeating analog input signal into a time series of digital amplitude values, the circuit comprising:
a differencer arranged to receive the analog input signal and a threshold input signal and arranged to output a differencer signal being the difference between the analog input signal and the threshold input signal;
a plurality of clocked comparators, each clocked comparator being arranged to sample the differencer signal upon receipt of a trigger signal and each clocked comparator being arranged to output and hold a quantized signal; and
for each clocked comparator, a decoder which is arranged to decode the quantized signal into a digital value.

### Claim 2 (depends on 1)

The range profile digitization circuit as claimed in claim 1, further comprising a continuous time amplifier downstream of the differencer, arranged to amplify the differencer signal.

### Claim 3 (depends on 1)

The range profile digitization circuit as claimed in claim 1, comprising a plurality of differencers, one for each clocked comparator and each arranged to receive the analog input signal and the threshold input signal and arranged to output a differencer signal being the difference between the analog input signal and the threshold input signal to its associated clocked comparator.

### Claim 4 (depends on 3)

The range profile digitization circuit as claimed in claim 3, wherein the differencer is an integral part of the clocked comparator circuit.

### Claim 5 (depends on 1)

The range profile digitization circuit as claimed in claim 1, comprising: for each clocked comparator: a plurality of decoders and a demultiplexer arranged to receive the amplified output from the clocked comparator and pass it to a selected one of said decoders based on a selector input.

### Claim 6 (depends on 5)

The range profile digitization circuit as claimed in claim 5, further comprising: a controller arranged to generate selector inputs for the demultiplexers, the controller being arranged to change the selector input of each demultiplexer every time the corresponding clocked comparator is triggered.

### Claim 7 (depends on 5)

The range profile digitization circuit as claimed in claim 5, wherein the controller is arranged to generate trigger signals for the plurality of clocked comparators and selector inputs for the demultiplexers; and wherein the controller is arranged to generate trigger signals that cycle through the plurality of clocked comparators a plurality of times; and wherein the controller is arranged to cycle through the demultiplexer selector inputs, changing each demultiplexer's selector input once per cycle of the trigger signals.

### Claim 8 (depends on 1)

The range profile digitization circuit as claimed in claim 1, further comprising: a controller arranged to generate trigger signals for the plurality of clocked comparators, the trigger signals being generated at regular time intervals.

### Claim 9 (depends on 8)

The range profile digitization circuit as claimed in claim 8, wherein the controller is arranged to generate a continuous stream of trigger signals comprising a plurality of cycles of the plurality of clocked comparators.

### Claim 10 (depends on 1)

The range profile digitization circuit as claimed in claim 1, wherein each clocked comparator is formed from a strong-arm latch.

### Claim 11 (depends on 1)

The range profile digitization circuit as claimed in claim 1, wherein the clocked comparator is arranged to generate a high or low output based on the polarity of the incoming signal.

### Claim 12

A method of range profile digitization for converting a repeating analog input signal into a time series of digital amplitude values, the digitization comprising:
taking the difference between the received analog input signal and a threshold input signal;
providing the difference signal to a plurality of clocked comparators;
each clocked comparator sampling the difference signal upon receipt of a trigger signal and outputting a quantized signal; and
for each clocked comparator, decoding the quantized signal to produce a digital value.

### Claim 13 (depends on 12)

The method as claimed in claim 12, further comprising amplifying the differencer signal in continuous time.

### Claim 14 (depends on 12)

The method as claimed in claim 12, comprising: for each clocked comparator: receiving the amplified output from the clocked comparator and passing it to a selected one of a plurality of decoders via a demultiplexer, based on a selector input.

### Claim 15 (depends on 14)

The method as claimed in claim 14, further comprising: generating selector inputs for the demultiplexers, and changing the selector input of each demultiplexer every time the corresponding clocked comparator is triggered.

### Claim 16 (depends on 12)

The method as claimed in claim 12, further comprising: generating trigger signals for the plurality of clocked comparators at regular time intervals.

### Claim 17 (depends on 16)

The method as claimed in claim 16, comprising generating a continuous stream of trigger signals comprising a plurality of cycles of the plurality of clocked comparators.

### Claim 18 (depends on 12)

The method as claimed in claim 12, comprising: generating trigger signals for the plurality of clocked comparators and generating selector inputs for the demultiplexers; and wherein the trigger signals cycle through the plurality of clocked comparators a plurality of times; and cycling through the demultiplexer selector inputs, changing each demultiplexer's selector input once per cycle of the trigger signals.