# US 12,191,878 B2 · Signal processing circuit

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- Number: US 12,191,878 B2
- Document ID: US12191878B2
- Status: Granted
- Kind: B2
- Application number: 17/995,329
- Filed: 2021-03-30
- Published: 2023-05-18
- Granted: 2025-01-07
- Earliest claimed: 2020-04-09
- Assignees: MINEBEA MITSUMI Inc.
- Applicants: MINEBEA MITSUMI Inc.
- Inventors: Takahiko Bando; Heisuke Nakashima; Fumihiro Inoue
- Web page: https://patentgrep.com/patent/US12191878B2

## CPC

- H03H 19/004: {Switched capacitor networks}
- H03M 1/1245: {Details of sampling arrangements or methods}
- H03F 3/45475: {using IC blocks as the active amplifying circuit}
- H03F 3/45596: {by offset reduction}
- H03M 1/181: {in feedback mode, i.e. by determining the range to be selected from one or more previous digital output values}
- H03F 2203/45514: the FBC comprising one or more switched capacitors, and being coupled between the LC and the IC
- H03M 1/687: {Segmented, i.e. the more significant bit converter being of the unary decoded type and the less significant bit converter being of the binary weighted type}
- H03M 1/802: {using capacitors, e.g. neuron-mos transistors, charge coupled devices}
- H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H03F: AMPLIFIERS

## Abstract

A signal processing circuit includes a first sampling capacitor and a second sampling capacitor that are connected for an input signal path of an analog signal, and a signal processor configured to perform predetermined processing on the analog signal sampled by the first sampling capacitor and the analog signal sampled by the second sampling capacitor. The sampling of the analog signal transmitted to one capacitor of the first sampling capacitor and the second sampling capacitor, and the predetermined processing performed by the signal processor on the analog signal sampled by another capacitor of the first sampling capacitor and the second sampling capacitor can be performed in parallel.

## Claims

### Claim 1

A signal processing circuit comprising:
a first sampling capacitor and a second sampling capacitor that are connected for an input signal path of an analog signal;
an offset adjustment circuit, and
a signal processor configured to perform predetermined processing on the analog signal sampled by the first sampling capacitor and the analog signal sampled by the second sampling capacitor,
wherein the sampling of the analog signal transmitted to one capacitor of the first sampling capacitor and the second sampling capacitor, and the predetermined processing performed by the signal processor on the analog signal sampled by another capacitor of the first sampling capacitor and the second sampling capacitor can be performed in parallel,
wherein the signal processor is an amplifier and the predetermined processing is amplification processing using a feedback capacitor, and
wherein the offset adjustment circuit is provided in a stage prior to the amplifier and is configured to adjust an offset amount of the analog signal to be amplified by the amplifier.

### Claim 2 (depends on 1)

The signal processing circuit as claimed in claim 1,
wherein a first period and a second period alternately occur,
wherein in the first period, the analog signal is sampled by the first sampling capacitor and the predetermined processing is performed by the signal processor on the analog signal sampled by the second sampling capacitor, and
wherein in the second period, the analog signal is sampled by the second sampling capacitor and the predetermined processing is performed by the signal processor on the analog signal sampled by the first sampling capacitor.

### Claim 3 (depends on 2)

The signal processing circuit as claimed in claim 2,
wherein in the first period, by turning on a plurality of first switches, the input signal path is connected to the first sampling capacitor and the second sampling capacitor is connected to the signal processor, and
wherein in the second period, by turning on a plurality of second switches, the input signal path is connected to the second sampling capacitor and the first sampling capacitor is connected to the signal processor.

### Claim 4 (depends on 1)

The signal processing circuit as claimed in claim 1, wherein a data rate of the analog signal that is output is twice greater than a data rate obtained when the sampling is performed by either the first sampling capacitor or the second sampling capacitor only.

### Claim 5 (depends on 1)

The signal processing circuit as claimed in claim 1, wherein the signal processor is an averaging filter and the predetermined processing is averaging filter processing.

### Claim 6

A signal processing circuit comprising:
a first sampling capacitor and a second sampling capacitor that are connected for a first input signal path of a first analog signal;
a plurality of first switches and a plurality of second switches;
a first feedback capacitor connected in series to the first sampling capacitor and a second feedback capacitor connected in series to the second sampling capacitor; and
a signal processor configured to perform predetermined processing on the first analog signal sampled by the first sampling capacitor and the first analog signal sampled by the second sampling capacitor,
wherein the sampling of the first analog signal transmitted to one capacitor of the first sampling capacitor and the second sampling capacitor, and the predetermined processing performed by the signal processor on the first analog signal sampled by another capacitor of the first sampling capacitor and the second sampling capacitor can be performed in parallel;
wherein a first period and a second period alternately occur;
wherein in the first period, the first analog signal is sampled by the first sampling capacitor and the predetermined processing is performed by the signal processor on the first analog signal sampled by the second sampling capacitor;
wherein in the second period, the first analog signal is sampled by the second sampling capacitor and the predetermined processing is performed by the signal processor on the first analog signal sampled by the first sampling capacitor;
wherein in the first period, by turning on the plurality of first switches, the first input signal path is connected to the first sampling capacitor and the second sampling capacitor is connected to the signal processor;
wherein in the second period, by turning on the plurality of second switches, the first input signal path is connected to the second sampling capacitor and the first sampling capacitor is connected to the signal processor;
wherein the signal processor is an amplifier and the predetermined processing is amplification processing using the first feedback capacitor and the second feedback capacitor;
wherein in the first period, by turning on the plurality of first switches, the first analog signal sampled by the second sampling capacitor is transferred to the second feedback capacitor; and
wherein in the second period, by turning on the plurality of second switches, the first analog signal sampled by the first sampling capacitor is transferred to the first feedback capacitor.

### Claim 7 (depends on 6)

The signal processing circuit as claimed in claim 6, wherein a data rate of the first analog signal that is output is twice greater than a data rate obtained when the sampling is performed by either the first sampling capacitor or the second sampling capacitor only.

### Claim 8 (depends on 6)

The signal processing circuit as claimed in claim 6, further comprising an offset adjustment circuit that is provided in a stage prior to the amplifier and that is configured to adjust an offset amount of the first analog signal to be amplified by the amplifier.

### Claim 9 (depends on 6)

The signal processing circuit as claimed in claim 6, further comprising:
a third sampling capacitor and a fourth sampling capacitor that are connected for a second input signal path of a second analog signal;
a third feedback capacitor connected in series to the third sampling capacitor and a fourth feedback capacitor connected in series to the fourth sampling capacitor;
a first output terminal that outputs the first analog signal processed by the signal processor; and
a second output terminal that outputs the second analog signal processed by the signal processor;
wherein the signal processor is configured to perform the predetermined processing on the second analog signal sampled by the third sampling capacitor and the second analog signal sampled by the fourth sampling capacitor,
wherein in the first period, the second analog signal is sampled by the third sampling capacitor and the predetermined processing is performed by the signal processor on the second analog signal sampled by the fourth sampling capacitor;
wherein in the second period, the second analog signal is sampled by the fourth sampling capacitor and the predetermined processing is performed by the signal processor on the second analog signal sampled by the third sampling capacitor;
wherein in the first period, by turning on the first switches, the second input signal path is connected to the third sampling capacitor, and the fourth sampling capacitor is connected to the signal processor, and
wherein in the second period, by turning on the second switches, the second input signal path is connected to the fourth sampling capacitor, and the third sampling capacitor is connected to the signal processor.