# US 12,191,869 B2 · Control circuit for an electronic converter, related integrated circuit, electronic converter and method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,191,869 B2 - Document ID: US12191869B2 - Status: Granted - Kind: B2 - Application number: 17/982,712 - Filed: 2022-11-08 - Published: 2023-05-25 - Granted: 2025-01-07 - Earliest claimed: 2021-11-19 - Assignees: STMicroelectronics S.r.l. - Applicants: STMicroelectronics S.r.l. - Inventors: Alessandro Bertolini; Alberto Cattani; Alessandro Gasparini - Web page: https://patentgrep.com/patent/US12191869B2 ## CPC - H02M 3/157: with digital control - H03L 7/0991: {the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider (H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814)} - H02M 1/0025: {Arrangements for modifying reference values, feedback values or error values in the control loop of a converter} - H02M 3/1566: {with means for compensating against rapid load changes, e.g. with auxiliary current source, with dual mode control or with inductance variation} - H02M 3/158: including plural semiconductor devices as final control devices for a single load - H03L 7/07: using several loops, e.g. for redundant clock signal generation - H03L 7/081: provided with an additional controlled phase shifter {(H03L7/0998 takes precedence)} - H03L 7/091: the phase or frequency detector using a sampling device (H03L7/087 takes precedence) - H03L 7/10: for assuring initial synchronisation or for broadening the capture range - H03K 5/14: by the use of delay lines (H03K5/133 takes precedence) - H03K 19/096: Synchronous circuits, i.e. using clock signals {(H03K19/01728, H03K19/01855 take precedence)} - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract In a control circuit for a switching stage of an electronic converter, a phase detector generates a drive signal in response to a phase difference between first and second clock signals. The first and second clock signals are generated by first and second current-controlled oscillators, respectively. An operational transconductance amplifier generates first and second control currents in response to a difference between a reference and a feedback of the electronic converter, with the first and second currents applied to control the first and second current-controlled oscillators. In response to a switching clock having a first state, a switching circuit applies first and second bias currents to the control inputs of the first and second current-controlled oscillators, respectively. Conversely, in response to the switching clock having a second state, the switching circuit applies the second and first bias currents to the control inputs of the first and second current-controlled oscillators, respectively. ## Claims ### Claim 1 A control circuit for a switching stage of an electronic converter configured to provide an output voltage, the control circuit comprising: a first terminal configured to provide a drive signal to a corresponding electronic switch of said switching stage; a second terminal configured to receive a first feedback signal proportional to said output voltage from a feedback circuit; a driver circuit configured to generate said drive signal as a function of a Pulse-Width Modulation (PWM) signal; and a PWM signal generator circuit configured to generate said PWM signal as a function of said first feedback signal and a reference voltage, wherein said PWM signal generator circuit comprises: a first current-controlled oscillator having an input terminal configured to receive a first current and generate a first clock signal as a function of said first current; a second current-controlled oscillator having an input terminal configured to receive a second current and generate a second clock signal as a function of said second current; a first operational transconductance amplifier configured to provide at a first amplifier output a third current indicative of a difference between said reference voltage and said first feedback signal, wherein said first amplifier output of said first operational transconductance amplifier is connected to said input terminal of said first current-controlled oscillator; and a phase detector having inputs coupled to said first oscillator and said second oscillator and providing at an output said PWM signal; wherein said PWM signal generator circuit further comprises: a first bias current generator configured to provide a first bias current at a first bias output; a second bias current generator configured to provide a second bias current at a second bias output; and a switching circuit configured to receive a switch clock signal and: when a logic level of said switch clock signal has a first logic level, connect the first bias output of said first bias current generator to the input terminal of said first current-controlled oscillator and connect the second bias output of said second bias current generator to the input terminal of said second current-controlled oscillator, and when the logic level of said switch clock signal has a second logic level, connect the first bias output of said first bias current generator to the input terminal of said second current-controlled oscillator and connect the second bias output of said second bias current generator to the input terminal of said first current-controlled oscillator. ### Claim 2 (depends on 1) The control circuit according to claim 1, wherein said switch clock signal is derived from said first clock signal or said second clock signal. ### Claim 3 (depends on 2) The control circuit according to claim 2, wherein said switch clock signal corresponds to one of said first clock signal or said second clock signal. ### Claim 4 (depends on 1) The control circuit according to claim 1, wherein said PWM signal generator circuit further comprises: a first delay line connected between said first current-controlled oscillator and said phase detector, and a second delay line connected between said second current-controlled oscillator and said phase detector. ### Claim 5 (depends on 4) The control circuit according to claim 4, wherein one or more of said first delay line and second delay line is driven as a function of the difference between said reference voltage and said first feedback signal. ### Claim 6 (depends on 4) The control circuit according to claim 4, comprising a terminal configured to receive from an analog differentiator a second feedback signal proportional to a derivative of said output voltage, and wherein one or more of said first delay line and second delay line is driven as a function of the difference between said reference voltage and said second feedback signal. ### Claim 7 (depends on 6) The control circuit according to claim 6, comprising at least one of: said one or more electronic switches of said switching stage; said feedback circuit; and said analog differentiator. ### Claim 8 (depends on 6) The control circuit according to claim 6, wherein each of said first delay line and said second delay line is a current-controlled delay line, and wherein said PWM signal generator circuit further comprises: a second operational transconductance amplifier configured to generate a fourth current indicative of a difference between said reference voltage and said first feedback signal; a third operational transconductance amplifier configured to generate a fifth current indicative of a difference between said reference voltage and said second feedback signal; wherein said fourth current and said fifth current are provided to one or more of the first delay line and the second delay line. ### Claim 9 (depends on 1) The control circuit according to claim 1, wherein said first operational transconductance amplifier is a differential operational transconductance amplifier configured to provide at a second amplifier output a sixth current, wherein a difference between said sixth current and said third current is proportional to a difference between a reference voltage and said first feedback signal, and wherein said second amplifier output of said first operational transconductance amplifier is connected to said input terminal of said second current-controlled oscillator. ### Claim 10 (depends on 1) The control circuit according to claim 1, wherein said electronic converter is a buck or boost converter. ### Claim 11 (depends on 1) The control circuit according to claim 1, where a frequency of the switch clock signal is outside a bandwidth of a control loop for the control circuit. ### Claim 12 (depends on 1) An integrated circuit comprising a control circuit according to claim 1. ### Claim 13 (depends on 1) An electronic converter, comprising: a switching stage, and a control circuit according to claim 1. ### Claim 14 A control circuit for a switching stage of an electronic converter configured to generate an output voltage, comprising: a feedback circuit configured to generate a feedback signal from said output voltage; an operational transconductance amplifier configured to generate, in response to a difference between a reference voltage and said feedback signal, a first output current and a second output current; a first current-controlled oscillator having an input coupled to receive the first output current and configured to generate a first clock signal; a second current-controlled oscillator having an input coupled to receive the second output current and configured to generate a second clock signal; a phase detector circuit configured to generate a drive signal for the switching stage of the electronic converter in response to a phase difference between the first and second clock signals; a first bias current generator configured to generate a first bias current; a second bias current generator configured to generate a second bias current; and a switching circuit controlled by a switch clock signal to: when the switch clock signal has a first logic level, apply the first bias current to the input of said first current-controlled oscillator and apply the second bias current to the input of the said second current-controlled oscillator, and when the switch clock signal has a second logic level, apply the second bias current to the input of said first current-controlled oscillator and apply the first bias current to the input of the said second current-controlled oscillator. ### Claim 15 (depends on 14) The control circuit according to claim 14, wherein a frequency of the switch clock signal is outside a bandwidth of a control loop for the control circuit. ### Claim 16 (depends on 14) The control circuit according to claim 14, wherein said switch clock signal is derived from said first clock signal. ### Claim 17 (depends on 14) The control circuit according to claim 14, wherein said switch clock signal is derived from said second clock signal. ### Claim 18 (depends on 14) The control circuit according to claim 14, wherein said switch clock signal corresponds to said first clock signal. ### Claim 19 (depends on 14) The control circuit according to claim 14, wherein said switch clock signal corresponds to said second clock signal. ### Claim 20 (depends on 14) The control circuit according to claim 14, wherein said electronic converter is a buck or boost converter.