# US 12,191,868 B2 · Frequency-locked and phase-locked loop-based clock glitch detection for security

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- Number: US 12,191,868 B2
- Document ID: US12191868B2
- Status: Granted
- Kind: B2
- Application number: 18/595,042
- Filed: 2024-03-04
- Published: 2024-06-20
- Granted: 2025-01-07
- Earliest claimed: 2022-05-25
- Assignees: NVIDIA Corporation
- Applicants: NVIDIA Corporation
- Inventors: Sanquan Song; Stephen G. Tell; Nikola Nedovic
- Web page: https://patentgrep.com/patent/US12191868B2

## CPC

- H03L 7/099: concerning mainly the controlled oscillator of the loop
- H03L 7/0995: {the oscillator comprising a ring oscillator}
- H03K 5/1252: Suppression or limitation of noise or interference (specially adapted for transmission systems H04B15/00, H04L25/08)
- H03L 7/0891: {the up-down pulses controlling source and sink current generators, e.g. a charge pump}
- H03L 7/091: the phase or frequency detector using a sampling device (H03L7/087 takes precedence)
- H03L 7/093: using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A glitch detection device includes an oscillator to generate multiple local clocks of multiple different phases and a sampling circuit to oversample, using the multiple local clocks, a system clock to generate multiple samples of the system clock. The device further includes a glitch detector to monitor a variation in pulse width of the system clock based on counting the multiple samples and to report a glitch in response to detecting a variation in the pulse width that exceeds a threshold value.

## Claims

### Claim 1

A glitch detection device comprising:
an oscillator to generate multiple local clocks of multiple different phases;
a sampling circuit to oversample, using the multiple local clocks, a system clock to generate multiple samples of the system clock; and
a glitch detector coupled to the sampling circuit, the glitch detector to:
monitor a variation in pulse width of the system clock based on counting the multiple samples; and
report a glitch in response to detecting a variation in the pulse width that exceeds a threshold value.

### Claim 2 (depends on 1)

The glitch detection device of claim 1, wherein the glitch detector comprises:
multiple counters, one counter to count each of the multiple samples;
a summer to combine values of the multiple counters and generate duty cycle measurements of pulses of the system clock; and
glitch detector logic to detect the variation in pulse width based on the duty cycle measurements.

### Claim 3 (depends on 2)

The glitch detection device of claim 2, further comprising:
a level shifter coupled to the oscillator to translate the multiple local clocks to a logic level of the sampling circuit; and
a crossover circuit coupled between the sampling circuit and the multiple counters, the crossover circuit to merge multiple phases of the multiple samples into a single-phase domain and provide a clock of the single-phase domain to the multiple counters.

### Claim 4 (depends on 1)

The glitch detection device of claim 1, further comprising:
a loop filter coupled between the glitch detector and the oscillator, the loop filter to variably adjust the oscillator based on a frequency of each of the multiple samples to control an output frequency of each of the multiple different phases of the oscillator, wherein the loop filter is configured to lock onto a frequency comprising a multiple of the system clock, and wherein the loop filter comprises:
a subtractor to determine a difference between a measured pulse width of the system clock and a target multiple of a frequency of the system clock; and
a first order digital filter coupled between the subtractor and the oscillator.

### Claim 5 (depends on 4)

The glitch detection device of claim 4, further comprising a supply regulator to convert a chip supply voltage to an oscillator supply voltage, wherein the loop filter is to variably adjust the oscillator supply voltage based on a frequency of each of the multiple samples to control the output frequency of each of the multiple different phases.

### Claim 6 (depends on 5)

The glitch detection device of claim 5, further comprising:
multiple first transistors coupled to the chip supply voltage, wherein a gate of each of the multiple first transistors is coupled to an output of the loop filter;
a second transistor coupled between the multiple first transistors and the oscillator supply voltage; and
a threshold voltage (VT)-based bias generator comprising a current mirror that generates an output voltage, to drive a second gate of the second transistor, based on a level of the chip supply voltage.

### Claim 7 (depends on 5)

The glitch detection device of claim 5, wherein the oscillator comprises:
an oscillator capacitor coupled to the supply regulator, the oscillator capacitor to hold the oscillator supply voltage;
a multiple-stage ring oscillator; and
multiple banks of loading capacitors, one coupled to each stage of the multiple-stage ring oscillator.

### Claim 8 (depends on 7)

The glitch detection device of claim 7, further comprising a supply difference detector (SDD)-based auto-tuner coupled to the multiple banks of capacitors, the SDD-based auto-tuner to:
detect that a difference between the chip supply voltage and the oscillator supply voltage drops below a threshold value; and
in response to the detection, turn off one or more loading capacitors of identical capacitance from each of the multiple banks of loading capacitors to fine-tune the multiple local clocks in response to process, voltage, temperature (PVT) variations.

### Claim 9 (depends on 7)

The glitch detection device of claim 7, further comprising a droop compensation circuit coupled to the oscillator capacitor, the droop compensation circuit to increase the oscillator supply voltage in response to detecting a noise-based droop in the oscillator supply voltage relative to the chip supply voltage.

### Claim 10 (depends on 4)

The glitch detection device of claim 4, wherein the loop filter is a phase-locked loop (PLL) filter, further comprising:
a phase frequency detector (PFD) coupled between the oscillator and the system clock, the PFD to lock onto a phase of the system clock or output a digital error pulse; and
a charge pump coupled between the PFD and the PLL filter, the charge pump to convert the digital error pulse to an analog error current that is provided to the PLL filter.

### Claim 11 (depends on 1)

The glitch detection device of claim 1, wherein the oscillator is one of a voltage-controlled oscillator (VCO), a supply-regulated ring oscillator, a current starving ring oscillator, a digitally-controlled ring oscillator, or an inductive-capacitive (LC) oscillator.

### Claim 12

A computing system comprising:
an external oscillator that generates a system clock; and
a die coupled to the external oscillator, the die comprising:
an internal oscillator to generate multiple local clocks of multiple different phases;
a sampling circuit to oversample, using the multiple local clocks, the system clock to generate multiple samples of the system clock; and
a glitch detector coupled to the sampling circuit, the glitch detector to:
monitor a variation in pulse width of the system clock based on counting the multiple samples; and
report a glitch in response to detecting a variation in the pulse width exceeds a threshold value.

### Claim 13 (depends on 12)

The computing system of claim 12, wherein the glitch detector comprises:
multiple counters, one counter to count each of the multiple samples;
a summer to combine values of the multiple counters and generate duty cycle measurements of pulses of the system clock; and
glitch detector logic to detect the variation in pulse width based on the duty cycle measurements.

### Claim 14 (depends on 13)

The computing system of claim 13, wherein the die further comprises:
a level shifter coupled to the internal oscillator to translate the multiple local clocks to a logic level of the sampling circuit; and
a crossover circuit coupled between the sampling circuit and the multiple counters, the crossover circuit to merge multiple phases of the multiple samples into a single-phase domain and provide a clock of the single-phase domain to the multiple counters.

### Claim 15 (depends on 12)

The computing system of claim 12, wherein the die further comprises:
a loop filter coupled between the glitch detector and the internal oscillator, the loop filter to variably adjust the internal oscillator based on a frequency of each of the multiple samples to control an output frequency of each of the multiple different phases of the internal oscillator, wherein the loop filter is configured to lock onto a frequency comprising a multiple of the system clock, and wherein the loop filter comprises:
a subtractor to determine a difference between a measured pulse width of the system clock and a target multiple of a frequency of the system clock; and
a first order digital filter coupled between the subtractor and the internal oscillator.

### Claim 16 (depends on 15)

The computing system of claim 15, wherein the die further comprises a supply regulator to convert a chip supply voltage to an oscillator supply voltage, wherein the loop filter is to variably adjust the oscillator supply voltage based on a frequency of each of the multiple samples to control the output frequency of each of the multiple different phases.

### Claim 17 (depends on 16)

The computing system of claim 16, wherein the die further comprises:
multiple first transistors coupled to the chip supply voltage, wherein a gate of each of the multiple first transistors is coupled to an output of the loop filter;
a second transistor coupled between the multiple first transistors and the oscillator supply voltage; and
a threshold voltage (VT)-based bias generator comprising a current mirror that generates an output voltage, to drive a second gate of the second transistor, based on a level of the chip supply voltage.

### Claim 18 (depends on 16)

The computing system of claim 16, wherein the internal oscillator comprises:
an oscillator capacitor coupled to the supply regulator, the oscillator capacitor to hold the oscillator supply voltage;
a multiple-stage ring oscillator; and
multiple banks of loading capacitors, one coupled to each stage of the multiple-stage ring oscillator.

### Claim 19 (depends on 18)

The computing system of claim 18, wherein the die further comprises a supply difference detector (SDD)-based auto-tuner coupled to the multiple banks of capacitors, the SDD-based auto-tuner to:
detect that a difference between the chip supply voltage and the oscillator supply voltage drops below a threshold value; and
in response to the detection, turn off one or more loading capacitors of identical capacitance from each of the multiple banks of loading capacitors to fine-tune the multiple local clocks in response to process, voltage, temperature (PVT) variations.

### Claim 20 (depends on 19)

The computing system of claim 19, wherein the die further comprises a droop compensation circuit coupled to the oscillator capacitor, the droop compensation circuit to increase the oscillator supply voltage in response to detecting a noise-based droop in the oscillator supply voltage relative to the chip supply voltage.

### Claim 21 (depends on 15)

The computing system of claim 15, wherein the loop filter is a phase-locked loop (PLL) filter, wherein the die further comprises:
a phase frequency detector (PFD) coupled between the oscillator and the system clock, the PFD to lock onto a phase of the system clock or output a digital error pulse; and
a charge pump coupled between the PFD and the PLL filter, the charge pump to convert the digital error pulse to an analog error current that is provided to the PLL filter.

### Claim 22 (depends on 12)

The computing system of claim 12, wherein the internal oscillator is one of a voltage-controlled oscillator (VCO), a supply-regulated ring oscillator, a current starving ring oscillator, a digitally-controlled ring oscillator, or an inductive-capacitive (LC) oscillator.

### Claim 23

A method of operating a glitch detection circuit comprising an oscillator, a sampling circuit, and digital logic for controlling the oscillator, the method of operating the glitch detection circuit comprising a plurality of operations comprising:
generating, by the oscillator, multiple local clocks of multiple different phases;
oversampling, by the sampling circuit using the multiple local clocks, a system clock to generate multiple samples of the system clock;
monitoring, by a glitch detector of the digital logic, a variation in pulse width of the system clock based on counting the multiple samples; and
reporting, by the glitch detector, a glitch in response to detecting a variation in the pulse width that exceeds a threshold value.