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US 12,191,866 B2Granted
Linear prediction to suppress spurs in a digital phase-locked loop
OwnerKannanthodath V. Jayakumarinventor
Life of this patent
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Abstract
A technique uses linear prediction to determine the location of spurious content in a digital phase-locked loop and suppresses the spurious content from propagating to the clock output. In at least one embodiment, the technique implements an iterative (e.g., recursive) computation.
Claims24
A method for generating a clock signal using utilizing a digital phase-locked loop, the method comprising:
- filtering a digital signal of the digital phase-locked loop using utilizing an all-zero filter having P weights, the P weights corresponding to P zeros of the all-zero filter at frequencies of P spurs in the digital signal, P being an integer greater than one.
A digital phase-locked loop comprising:
- a time-to-digital converter configured to generate a digital signal based on an input clock signal, the digital phase-locked loop being configured to generate a phase-adjusted clock signal based on the digital signal and a feedback clock signal utilizing a frequency-divided clock signal;
- and
- an all-zero filter coupled between the time-to-digital converter and an output of the digital phase-locked loop, the all-zero filter having P weights, the P weights corresponding to P zeros at frequencies of P spurs in the digital signal, P being an integer greater than one.
A method for generating a clock signal utilizing a digital phase-locked loop, the method comprising:
- determining P weights of an all-pole transfer function having P poles corresponding to locations of spurious energy in a digital signal of the digital phase-locked loop, the P weights being determined based on the digital signal of the digital phase-locked loop, P being an integer greater than one.
Dependencies are inferred from the claim text.