# US 12,191,865 B2 · Phase lock loop (PLL) synchronization > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,191,865 B2 - Document ID: US12191865B2 - Status: Granted - Kind: B2 - Application number: 18/225,477 - Filed: 2023-07-24 - Published: 2023-11-23 - Granted: 2025-01-07 - Earliest claimed: 2019-05-14 - Assignees: Space Exploration Technologies Corp. - Applicants: Space Exploration Technologies Corp.; Iliana Ghazali - Inventors: David Francois Jacquet; Mostafa Ghazali; Masoud Kahrizi; Andras Tantos - Web page: https://patentgrep.com/patent/US12191865B2 ## CPC - H03L 7/07: using several loops, e.g. for redundant clock signal generation - G06F 1/10: Distribution of clock signals {, e.g. skew} - H01Q 3/42: using frequency-mixing {(H01Q3/2676 takes precedence)} - H03L 7/1976: {using a phase accumulator for controlling the counter or frequency divider} - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H01Q: ANTENNAS, i.e. RADIO AERIALS (radiators or antennas for microwave heating H05B6/72) ## Abstract In an embodiment, an apparatus includes one or more timing components configured to generate a reference time signal based on a timing signal and a reference clock signal. The apparatus includes phase lock loop (PLL) configured to generate a synchronized output clock signal based on the reference clock signal and the reference time signal. ## Claims ### Claim 1 An apparatus comprising: one or more timing components configured to generate a reference time signal based on a timing signal and a reference clock signal; and a phase lock loop (PLL) configured to generate a synchronized output clock signal based on the reference clock signal and the reference time signal, wherein one or more timing components are configured to generate a synchronization signal to trigger phase synchronization of the PLL if the reference time signal equals a pre-set reference time signal count value and the PLL is in a locked state. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the reference time signal is generated at a first particular cycle of the reference clock signal, wherein synchronization of the PLL is initiated during a second particular cycle of the reference clock signal, and wherein the first particular cycle of the reference clock signal is a different cycle than the second particular cycle of the reference clock signal. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the PLL comprises a sigma delta modulator (SDM). ### Claim 4 (depends on 3) The apparatus of claim 3, wherein the PLL comprises a particular sigma-delta sequence. ### Claim 5 (depends on 3) The apparatus of claim 3, wherein: the PLL further comprises a first feedback divider controlled by a first divider ratio associated with the SDM. ### Claim 6 (depends on 4) The apparatus of claim 4, wherein synchronization of the PLL comprises synchronizing a starting point of the particular sigma-delta sequence in the PLL. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the PLL includes a feedback divider electrically coupled to a sigma delta modulator (SDM), and wherein the SDM is configured to define a divider ratio sequence of the feedback divider. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein the SDM includes a sigma-delta sequence, and wherein the divider ratio sequence is a function of the sigma-delta sequence. ### Claim 9 (depends on 7) The apparatus of claim 7, wherein the feedback divider comprises a plurality of selective divider modulators, and wherein a first selective divider modulator of the plurality of selective divider modulators is different from a second selective divider modulator of the plurality of selective divider modulators. ### Claim 10 (depends on 1) The apparatus of claim 1, wherein the PLL comprises a fractional mode PLL. ### Claim 11 (depends on 1) The apparatus of claim 1, further comprising: a clock PLL configured to generate and provide a second reference clock signal at a higher frequency than the reference clock signal, wherein one or more timing components are further configured to generate a third reference time signal based on the reference time signal and the second reference clock signal, wherein the third reference time signal specifies a count of a number of cycles of the second reference clock signal starting from a particular cycle of the second reference clock signal, and wherein the PLL is synchronized based on the third reference time signal. ### Claim 12 (depends on 11) The apparatus of claim 11, wherein the third reference time signal has a finer count resolution than the reference time signal within a same time period. ### Claim 13 (depends on 1) The apparatus of claim 1, wherein the timing signal, the reference time signal, and the synchronized output clock signal are periodic signals, wherein a period of the reference time signal is greater than a period of the timing signal and wherein the period of the timing signal is greater than a period of the synchronized output clock signal. ### Claim 14 (depends on 1) The apparatus of claim 1, wherein the PLL is reset based on a combination of an active state of a synchronization enable signal and an active state of the reference time signal, wherein an inactive state of the synchronization enable signal prevents the reference time signal from resetting the PLL. ### Claim 15 An apparatus comprising: a phase lock loop (PLL), wherein the PLL includes a sigma delta modulator (SDM), and wherein the PLL is configured to generate an output clock signal based on a reference clock signal, wherein the SDM is reset based on the reference clock signal, a timing signal, and a reference time signal; and one or more timing components configured to generate the reference time signal based on a timing signal and the reference clock signal; and a clock PLL configured to generate and provide a second reference clock signal at a higher frequency than the reference clock signal, wherein: the one or more timing components are configured to generate a second reference time signal based on the reference time signal and the second reference clock signal; the second reference time signal specifies a count of a number of cycles of the second reference clock signal starting from a particular cycle of the second reference clock signal; and the SDM is reset based on the second reference time signal. ### Claim 16 (depends on 15) The apparatus of claim 15, wherein the SDM is reset based on a particular cycle of the reference clock signal when the PLL is in a locked state. ### Claim 17 (depends on 15) The apparatus of claim 15, wherein the SDM includes a sigma-delta sequence, and wherein resetting of the SDM comprises aligning the sigma-delta sequence of the SDM to a particular point in the sigma-delta sequence. ### Claim 18 (depends on 17) The apparatus of claim 17, further configured to: receive the timing signal and the reference clock signal; generate the reference time signal based on the timing signal and the reference clock signal; and reset the SDM based on the reference time signal. ### Claim 19 (depends on 18) The apparatus of claim 18, wherein the reference time signal is generated within a particular cycle of the reference clock signal. ### Claim 20 (depends on 15) The apparatus of claim 15, wherein the second reference time signal has a finer count resolution than the reference time signal for a same time period. ### Claim 21 An apparatus comprising: a phase lock loop (PLL), wherein the PLL includes a sigma delta modulator (SDM), wherein the PLL is configured to generate an output clock signal based on a reference clock signal, wherein the SDM is reset based on the reference clock signal, a timing signal, and a reference time signal, and wherein the reference clock signal comprises a first reference clock signal and the PLL is configured to generate an output clock signal based on a reference clock signal; a counter configured to generate, based on a timing signal and the first reference clock signal, a first reference time signal indicative of a count of periods of the first reference clock signal; a second reference clock configured to generate a second reference clock signal having a second frequency different from a first frequency associated with the first reference clock signal; a clock generator configured to generate, based on the first reference clock signal, the second reference clock signal, and a phase selection, a third reference clock signal having a third frequency, wherein at least one or more of the third frequency or a phase shift of the third reference clock signal is different from the second reference clock signal; and a second counter configured to generate a third reference time signal indicative of sub-periods of the third reference clock signal in accordance with the phase selection, wherein the SDM is reset using the third reference time signal. ### Claim 22 (depends on 21) The apparatus of claim 21, wherein the second frequency is greater than the first frequency and the third frequency is less than the second frequency. ### Claim 23 (depends on 21) The apparatus of claim 21, wherein the third reference time signal indicates a number of phase increments for each period of the third reference clock signal that is 360 divided by a phase increment associated with the phase selection. ### Claim 24 (depends on 15) The apparatus of claim 15, further comprising one or more timing components configured to generate the reference time signal based on the timing signal and the reference clock signal, wherein the SDM is reset based on a combination of an active state of a synchronization enable signal and an active state of the reference time signal, wherein an inactive state of the synchronization enable signal prevents the reference time signal from resetting the SDM. ### Claim 25 (depends on 15) The apparatus of claim 15, wherein the timing signal, the reference time signal, and the output clock signal are periodic signals, wherein a period of the reference time signal is greater than a period of the timing signal and wherein the period of the timing signal is greater than a period of the output clock signal.