# US 12,191,864 B2 · Comparator with configurable operating modes

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- Number: US 12,191,864 B2
- Document ID: US12191864B2
- Status: Granted
- Kind: B2
- Application number: 18/186,855
- Filed: 2023-03-20
- Published: 2023-07-20
- Granted: 2025-01-07
- Earliest claimed: 2020-03-23
- Assignees: Analog Devices, Inc.
- Applicants: Analog Devices, Inc.
- Inventors: Christopher C. McQuilkin; Andrew Nathan Mort
- Web page: https://patentgrep.com/patent/US12191864B2

## CPC

- H03K 5/24: the characteristic being amplitude
- G01R 19/0038: {Circuits for comparing several input signals and for indicating the result of this comparison, e.g. equal, different, greater, smaller (comparing pulses or pulse trains according to amplitude)}
- G01R 31/31924: {Voltage or current aspects, e.g. driver, receiver}
- G01R 31/31932: {Comparators}
- G11C 7/062: {Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs}
- G11C 29/56012: {Timing aspects, clock generation, synchronisation}
- G11C 29/56016: {Apparatus features}
- H03K 5/01: Shaping pulses (discrimination against noise or interference H03K5/125)
- H03K 5/023: {using field effect transistors}
- H03K 5/2481: {with at least one differential stage}
- G01R 31/2834: {Automated test systems [ATE]; using microprocessors or computers (G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736)}
- G11C 2029/5602: {Interface to device under test}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A multiple operating-mode comparator system can be useful for high bandwidth and low power automated testing. The system can include a gain stage configured to drive a high impedance input of a comparator output stage, wherein the gain stage includes a differential switching stage coupled to an adjustable impedance circuit, and an impedance magnitude characteristic of the adjustable impedance circuit corresponds to a bandwidth characteristic of the gain stage. The comparator output stage can include a buffer circuit coupled to a low impedance comparator output node. The buffer circuit can provide a reference voltage for a switched output signal at the output node in a higher speed mode, and the buffer circuit can provide the switched output signal at the output node in a lower power mode.

## Claims

### Claim 1

A method comprising:
at an adjustable-power gain stage of a comparator system, receiving a differential input signal;
in response to the differential input signal, selectively processing the differential input signal to maintain a constant gain in a higher speed comparator mode and in a lower power comparator mode, and providing a gain stage output signal;
receiving the gain stage output signal at an output stage of the comparator system; and
in the higher speed comparator mode, opening a buffer input switch and closing a buffer output switch to provide a switched output signal at an output node of the comparator system, and
in the lower power comparator mode, closing the buffer input switch and opening the buffer output switch to provide a switching voltage at an input of a buffer circuit, and providing the switched output signal at the output node using the buffer circuit in response to the switching voltage.

### Claim 2 (depends on 1)

The method of claim 1, further comprising, in the higher speed comparator mode, using the buffer circuit to provide a fixed reference voltage at the output node.

### Claim 3 (depends on 1)

The method of claim 1, further comprising providing first and different second current signals to the buffer input switch and the buffer output switch, respectively, wherein the buffer input switch comprises a first differential pair of transistors and the buffer output switch comprises a second differential pair of transistors.

### Claim 4 (depends on 1)

The method of claim 1, wherein selectively processing the differential input signal to maintain a constant gain includes shunting a resistive network in the gain stage in the higher speed comparator mode, and applying the resistive network in the lower power comparator mode.

### Claim 5 (depends on 1)

The method of claim 1, wherein the gain stage comprises a differential pair circuit, and wherein the method further comprises changing a bandwidth characteristic of the gain stage using an adjustable impedance device to maintain a constant gain in the higher speed comparator mode and the lower power comparator mode.

### Claim 6 (depends on 1)

The method of claim 1, wherein receiving the differential input signal includes receiving the differential input signal using respective transistors of a differential pair, wherein the transistors are coupled to an adjustable bias current source; and
wherein selectively processing the differential input signal includes providing a lower magnitude current signal using the adjustable bias current source in the lower power comparator mode and providing a higher magnitude current signal using the adjustable bias current source in the higher speed comparator mode.

### Claim 7 (depends on 6)

The method of claim 6, wherein selectively processing the differential input signal to maintain a constant gain includes adjusting a resistance characteristic of a resistor network that is coupled to collector terminals of the transistors of the differential pair.

### Claim 8

A method comprising:
receiving a differential input signal at an adjustable-power gain stage of a comparator system;
providing a gain stage output signal from the gain stage by selectively processing the received differential input signal to maintain a constant gain in a higher speed comparator mode of the comparator system and in a lower power comparator mode of the comparator system; and
at an output stage of the comparator system, providing a switched output signal based on the gain stage output signal;
wherein providing the switched output signal based on the gain stage output signal includes:
in the lower power comparator mode, using the gain stage output signal as a control signal for a buffer circuit, and providing the switched output signal from the buffer circuit at an output node; and
in the higher speed comparator mode, using the buffer circuit to provide a reference voltage at the output node.

### Claim 9 (depends on 8)

The method of claim 8, wherein receiving the differential input signal includes receiving the differential input signal using respective transistors of a first differential pair.

### Claim 10 (depends on 9)

The method of claim 9, wherein selectively processing the received differential input signal includes adjusting a bias current for the first differential pair, wherein the bias current comprises a lower magnitude current signal in the lower power comparator mode and wherein the bias current comprises a higher magnitude current signal in the higher speed comparator mode.

### Claim 11 (depends on 9)

The method of claim 9, wherein selectively processing the received differential input signal includes adjusting a resistance characteristic of a resistor network that is coupled to collector terminals of the first differential pair.

### Claim 12 (depends on 11)

The method of claim 11, wherein selectively processing the received differential input signal includes adjusting a bias current for the first differential pair in coordination with adjusting the resistance characteristic of the resistor network.

### Claim 13 (depends on 12)

The method of claim 12, wherein the bias current comprises a lower magnitude current signal in the lower power comparator mode and wherein the bias current comprises a higher magnitude current signal in the higher speed comparator mode.

### Claim 14 (depends on 8)

The method of claim 8, wherein providing the switched output signal based on the gain stage output signal includes:
in the lower power comparator mode, processing the gain stage output signal using a first differential pair of transistors and a buffer circuit; and
in the higher speed comparator mode, processing the gain stage output signal using a different second differential pair of transistors.