# US 12,191,857 B2 · Memory device processing

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- Number: US 12,191,857 B2
- Document ID: US12191857B2
- Status: Granted
- Kind: B2
- Application number: 18/448,071
- Filed: 2023-08-10
- Published: 2024-04-04
- Granted: 2025-01-07
- Earliest claimed: 2018-10-16
- Applicants: Lodestar Licensing Group, LLC
- Inventors: Timothy P Finkbeiner; Troy D. Larsen
- Web page: https://patentgrep.com/patent/US12191857B2

## CPC

- H03K 19/1776: for memories
- G06F 3/0625: {Power saving in storage systems}
- G06F 3/0688: {Non-volatile semiconductor memory arrays}
- G06F 15/7821: {Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory}
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 7/1012: {Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating}
- G11C 11/401: forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 7/065: {Differential amplifiers of latching type}
- G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
- G11C 2207/002: Isolation gates, i.e. gates coupling bit lines to the sense amplifier
- G11C 2207/2245: Memory devices with an internal cache buffer
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

An example apparatus includes a memory device comprising a plurality of banks of memory cells. A particular bank of memory cells among the plurality of banks includes a system processor resident on a particular bank of the plurality of banks.

## Claims

### Claim 1

An apparatus, comprising:
a memory device comprising a system processor resident thereon; and
a plurality of memory banks resident on the memory device, wherein at least one memory bank of the plurality of memory banks comprises a bank processor resident thereon;
wherein the system processor is configured to orchestrate execution of processing-in-memory (PIM) instructions by the bank processor of the at least one memory bank without transferring data via an input/output (I/O) interface that couples the memory device to a host.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the system processor is a reduced instruction set computer (RISC) processor.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the system processor is a RISC-V processor.

### Claim 4 (depends on 2)

The apparatus of claim 2, wherein the bank processor of the at least one memory bank is a RISC-V processor.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the system processor is a RISC-V processor having increased processing capability as compared to the bank processor of the at least one memory bank.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the at least one memory bank of the plurality of memory banks includes an instruction cache.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the at least one memory bank of the plurality of memory banks includes a bank-to-bank transfer cache.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein the I/O interface is a double date rate (DDR) interface.

### Claim 9

An apparatus, comprising:
a host;
a memory device coupled to the host and comprising:
a system processor resident on the memory device; and
a plurality of memory banks comprising respective bank processors;
wherein the system processor is configured to orchestrate execution of processing-in-memory (PIM) instructions by the respective bank processors of the plurality of memory banks without transferring data via an input/output (I/O) interface that couples the memory device to the host.

### Claim 10 (depends on 9)

The apparatus of claim 9, further comprising a bank-to-bank transfer bus coupled to the plurality of memory banks via a periphery data path.

### Claim 11 (depends on 10)

The apparatus of claim 10, wherein the memory device comprises a direct memory access (DMA) component coupled to the periphery data path.

### Claim 12 (depends on 10)

The apparatus of claim 10, wherein the bank-to-bank transfer bus provides a data path over which data may be transferred between the plurality of memory banks.

### Claim 13 (depends on 9)

The apparatus of claim 9, wherein the system processor comprises a RISC-V processor.

### Claim 14 (depends on 9)

The apparatus of claim 9, wherein at least one of the respective bank processors comprises a RISC-V processor.

### Claim 15 (depends on 9)

The apparatus of claim 9, wherein the host comprises one or more of a computer, a smartphone, and an internet-of-things device.

### Claim 16 (depends on 9)

The apparatus of claim 9, wherein at least one of the plurality of memory banks includes a number of extended row address components configured to operate as caches for the system processor.

### Claim 17

An apparatus, comprising:
a host;
a memory device coupled to the host and comprising:
a plurality of memory banks comprising respective bank processors; and
a system processor resident on the memory device, wherein the system processor serves as a supervisory processing device to control operation of the respective bank processors in association with executing a program without transferring data via an input/output (I/O) interface that couples the memory device to the host.

### Claim 18 (depends on 17)

The apparatus of claim 17, wherein the memory device includes an instruction cache configured to store instructions for the system processor.

### Claim 19 (depends on 18)

The apparatus of claim 18, wherein the memory device includes a bank-to-bank transfer cache.

### Claim 20 (depends on 18)

The apparatus of claim 18, wherein the respective bank processors are RISC-V processors and wherein the instruction cache is configured to store RISC-V instructions.