# US 12,191,854 B2 · PPA improvement for voltage mode driver and on-die termination (ODT) > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,191,854 B2 - Document ID: US12191854B2 - Status: Granted - Kind: B2 - Application number: 17/949,990 - Filed: 2022-09-21 - Published: 2024-03-21 - Granted: 2025-01-07 - Earliest claimed: 2022-09-21 - Assignees: SanDisk Technologies LLC - Applicants: SanDisk Technologies LLC - Inventors: Nirav Natwarbhai Patel; Shiv Harit Mathur; Sai Ravi Teja Konakalla - Web page: https://patentgrep.com/patent/US12191854B2 ## CPC - H03K 19/0005: {Modifications of input or output impedance} - G11C 7/1048: {Data bus control circuits, e.g. precharging, presetting, equalising} - G11C 16/30: Power supply circuits - G11C 16/0483: {comprising cells having several storage transistors connected in series} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Systems and methods for improving the power, performance, and area (PPA) for a voltage mode driver and on die termination (ODT). A voltage mode driver having first and second circuits in a pulldown design. The first circuit has a plurality of nMOS devices in parallel, the plurality of nMOS devices being common to a first resistor. The second circuit is in parallel with the first circuit and has an nMOS device in series with a second resistor. The second circuit is configured to be enabled when the pulldown impedance of the first circuit, with the second circuit disabled and all of the nMOS devices of the first circuit turned on, is greater than a desired pulldown impedance. The voltage mode driver may also be a pullup design, or have both pulldown and pullup stages. ## Claims ### Claim 1 A voltage mode driver, comprising: a pull-down stage including: a first circuit having a plurality of nMOS devices in parallel, the plurality of nMOS devices being common to a first resistor; a second circuit in parallel with the first circuit and having an nMOS device in series with a second resistor; and X-2 additional circuits in parallel with the first and second circuits, each additional circuit having an additional nMOS device in series with an additional resistor, wherein the second circuit is configured to be enabled when a pulldown impedance of the first circuit, with the second circuit disabled and all of the nMOS devices of the first circuit turned on, is greater than a desired pulldown impedance, and wherein each of the first circuit through a Yth circuit are configured to be enabled when a condition is met that the pulldown impedance of the first through the (Y-1) th circuits, with the Yth circuit disabled and all of the nMOS devices of the first through the (Y-1) th circuits turned on, is greater than the desired pulldown impedance, and wherein X is an integer greater than 2, and Y is an integer greater than 1. ### Claim 2 (depends on 1) The voltage mode driver of claim 1, wherein a calibration algorithm is used to determine in one cycle whether the pulldown impedance of the first circuit, with the second circuit disabled and all of the nMOS devices of the first circuit turned on, is greater than the desired pulldown impedance or not. ### Claim 3 (depends on 1) The voltage mode driver of claim 1, wherein the voltage mode driver is implemented in a memory device. ### Claim 4 (depends on 1) The voltage mode driver of claim 1, wherein a calibration algorithm is used to determine in ceil (log (x)) cycles when the pulldown impedance of the first through the (Y-1) th circuits, with the Yth circuit disabled and all of the nMOS devices of the first through the (Y-1) th circuits turned on, is greater than the desired pulldown impedance, and wherein a binary sequence is used to determine within log (x) cycles the value of Y. ### Claim 5 (depends on 1) The voltage mode driver of claim 1, further comprising: a pull-up stage including: a third circuit having a plurality of pMOS devices in parallel, the plurality of pMOS devices being common to a third resistor; and a fourth circuit in parallel with the third circuit and having a pMOS device in series with a fourth resistor, wherein the fourth circuit is configured to be enabled when a pull-up impedance of the third circuit, with the fourth circuit disabled and all of the pMOS devices of the third circuit turned on, is greater than a desired pull-up impedance. ### Claim 6 (depends on 5) The voltage mode driver of claim 5, wherein a calibration algorithm is used to determine in one cycle when the pull-up impedance of the third circuit, with the fourth circuit disabled and all of the pMOS devices of the third circuit turned on, is greater than the desired pull-up impedance. ### Claim 7 (depends on 5) The voltage mode driver of claim 5, wherein the pull-up stage further comprises A-2 additional circuits in parallel with the third and fourth circuits, each additional circuit having an additional pMOS device in series with an additional resistor, wherein each of the third circuit through a Bth circuit are configured to be enabled when a condition is met that the pull-up impedance of the third circuit through the (B-1) th circuits, with the Bth circuit disabled and all of the pMOS devices of the third through the (B-1) th circuits turned on, is greater than the desired pull-up impedance, and wherein A is an integer greater than 2, and B is an integer greater than 1. ### Claim 8 (depends on 1) The voltage mode driver of claim 1, in which each nMOS device is one of a single device or a stacked device with same or different inputs being one of data, a calibration code, or a voltage reference. ### Claim 9 A voltage mode driver, comprising: a pull-down stage including: a first circuit having a plurality of nMOS devices in parallel, the plurality of nMOS devices being common to a first resistor; and X-1 additional circuits in parallel with the first circuit, each additional circuit having an additional nMOS device in series with an additional resistor, wherein each of the first circuit through a Yth additional circuit are configured to be enabled when a condition is met that the pulldown impedance of the first through the (Y-1) th additional circuits, with the Yth additional circuit disabled and all of the nMOS devices of the first through the (Y-1) th circuits turned on, is greater than the desired pulldown impedance, and wherein X is an integer greater than 2, and Y is an integer greater than 1. ### Claim 10 (depends on 9) The voltage mode driver of claim 9, wherein the voltage mode driver is implemented in a memory device. ### Claim 11 (depends on 9) The voltage mode driver of claim 9, wherein a calibration algorithm is used to determine in ceil (log (x)) cycles when the pulldown impedance of the first through the (Y-1) th circuits, with the Yth circuit disabled and all of the nMOS devices of the first through the (Y-1) th circuits turned on, is greater than the desired pulldown impedance, and wherein a binary sequence is used to determine within log (x) cycles the value of Y. ### Claim 12 (depends on 9) The voltage mode driver of claim 9, further comprising: a pull-up stage including: a third circuit having a plurality of pMOS devices in parallel, the plurality of pMOS devices being common to a third resistor; and a fourth circuit in parallel with the third circuit and having a pMOS device in series with a fourth resistor, wherein the fourth circuit is configured to be enabled when a pull-up impedance of the third circuit, with the fourth circuit disabled and all of the pMOS devices of the third circuit turned on, is greater than a desired pull-up impedance. ### Claim 13 (depends on 12) The voltage mode driver of claim 12, wherein a calibration algorithm is used to determine in one cycle when the pull-up impedance of the third circuit, with the fourth circuit disabled and all of the pMOS devices of the third circuit turned on, is greater than the desired pull-up impedance. ### Claim 14 (depends on 13) The voltage mode driver of claim 13, wherein the pull-up stage further comprises A-2 additional circuits in parallel with the third and fourth circuits, each additional circuit having an additional pMOS device in series with an additional resistor, wherein each of the third circuit through a Bth circuit are configured to be enabled when a condition is met that the pull-up impedance of the third circuit through the (B-1) th circuits, with the Bth circuit disabled and all of the pMOS devices of the third through the (B-1) th circuits turned on, is greater than the desired pull-up impedance, and wherein A is an integer greater than 2, and B is an integer greater than 1. ### Claim 15 (depends on 9) The voltage mode driver of claim 9, in which each nMOS device is one of a single device or a stacked device with same or different inputs being one of data, a calibration code, or a voltage reference.