# US 12,191,852 B2 · Multiplexing circuit, output stage, and semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,191,852 B2 - Document ID: US12191852B2 - Status: Granted - Kind: B2 - Application number: 18/518,640 - Filed: 2023-11-24 - Published: 2024-03-14 - Granted: 2025-01-07 - Earliest claimed: 2021-08-30 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company Ltd. - Inventors: Chin Hua Wen - Web page: https://patentgrep.com/patent/US12191852B2 ## CPC - H03K 17/693: Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00) - H03K 19/018585: {programmable} - H03K 17/6871: {the output circuit comprising more than one controlled field-effect transistor} - H03H 7/38: Impedance-matching networks - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P) ## Abstract A multiplexing circuit including a first type transistor, a second type transistor and an impedance circuit; a gate terminal of the first type transistor is configured to receive a control signal and free from receiving a clock signal; the second type transistor is coupled to the first type transistor, wherein a gate terminal of the second type transistor is configured to receive the clock signal, and the first type transistor is different from the second type transistor; the impedance circuit is arranged to provide an impedance between the gate terminal of the first type transistor and the second type transistor, wherein the impedance circuit is free from connecting to the gate terminal of the second type transistor. ## Claims ### Claim 1 A multiplexing circuit, comprising: a first type transistor, wherein a gate terminal of the first type transistor is configured to receive a control signal and free from receiving a clock signal; a second type transistor, coupled to the first type transistor, wherein a gate terminal of the second type transistor is configured to receive the clock signal, and the first type transistor is different from the second type transistor; and an impedance circuit arranged to provide an impedance between the gate terminal of the first type transistor and the second type transistor, wherein the impedance circuit is free from connecting to the gate terminal of the second type transistor. ### Claim 2 (depends on 1) The multiplexing circuit of claim 1, further comprising: an output terminal, coupled between the first type transistor and the second type transistor, wherein the impedance circuit is connect connected to the output terminal. ### Claim 3 (depends on 2) The multiplexing circuit of claim 2, wherein the impedance circuit includes a resistor, and a terminal of the resistor is connected to the gate terminal of the first type transistor while another terminal of the resistor is connected to the output terminal. ### Claim 4 (depends on 2) The multiplexing circuit of claim 2, wherein the multiplexing circuit is free from coupling a passive inductor to the output terminal of the multiplexing circuit. ### Claim 5 (depends on 2) The multiplexing circuit of claim 2, wherein the first type transistor is a P-type Metal Oxide Semiconductor (PMOS), a drain terminal of the PMOS is coupled to a first reference voltage, and a source terminal of the PMOS is coupled to the output terminal. ### Claim 6 (depends on 2) The multiplexing circuit of claim 2, wherein the second type transistor is an N-type Metal Oxide Semiconductor (NMOS), a drain terminal of the NMOS is coupled to the output terminal, and a source terminal of the NMOS is coupled to a second reference voltage. ### Claim 7 An output stage of a semiconductor device, coupled to an output port of the semiconductor device for receiving a transmission line and comprising: a multiplexing circuit, comprising: a first type transistor; a second type transistor, coupled to the first type transistor, wherein the first type transistor is different from the second type transistor; and an impedance circuit, arranged to provide an impedance between a gate terminal of the first type transistor and the second type transistor; an input circuit arranged to receive a first clock signal and a second clock signal, including a sub-output terminal, and the sub-output terminal is connected to a gate terminal of the second type transistor; and a driving circuit, coupled between the multiplexing circuit and the output port. ### Claim 8 (depends on 7) The output stage of claim 7, wherein the multiplexing circuit further comprises an output terminal coupled between the first type transistor and the second type transistor, and the impedance circuit is connected to the output terminal. ### Claim 9 (depends on 8) The output stage of claim 8, wherein the impedance circuit includes a resistor, and a terminal of the resistor is connected to the gate terminal of the first type transistor while another terminal of the resistor is connected to the output terminal. ### Claim 10 (depends on 8) The output stage of claim 8, wherein the multiplexing circuit is free from coupling a passive inductor to the output terminal. ### Claim 11 (depends on 8) The output stage of claim 8, wherein the first type transistor is a P-type Metal Oxide Semiconductor (PMOS), and the second type transistor is an N-type MOS (NMOS). ### Claim 12 (depends on 8) The output stage of claim 8, wherein a phase difference between the first clock signal and the second clock signal is 90 degrees. ### Claim 13 (depends on 8) The output stage of claim 8, wherein the input circuit comprises: a first stage, including: a first P-type Metal Oxide Semiconductor (PMOS), wherein a source terminal of the first PMOS is coupled to a first reference voltage, a drain terminal of the first PMOS is coupled to a connection terminal, and a gate terminal of the first PMOS is coupled to a first input terminal of the input circuit; a first N type MOS (NMOS), wherein a drain terminal of the first NMOS is coupled to the connection terminal, a source terminal of the first NMOS is coupled to a second terminal, and a gate terminal of the first NMOS is coupled to a second input terminal of the input circuit; and a second NMOS, wherein a drain terminal of the second NMOS is coupled to the second terminal, a source terminal of the second NMOS is coupled to a second reference voltage, and a gate terminal of the second NMOS is coupled to the first input terminal. ### Claim 14 (depends on 13) The output stage of claim 13, wherein the input circuit further comprises: a second stage, including: a second PMOS, wherein a source terminal of the second PMOS is coupled to the first reference voltage, a drain terminal of the second PMOS is coupled to a third terminal, and a gate terminal of the second PMOS is coupled to the connection terminal; a third PMOS, wherein a source terminal of the third PMOS is coupled to the third terminal, a drain terminal of the third PMOS is coupled to a fourth terminal, and a gate terminal of the third PMOS is configured to receive an input indicating signal; and a third NMOS, wherein a drain terminal of the third NMOS is coupled to the fourth terminal, a source terminal of the third NMOS is coupled to the second reference voltage, and a gate terminal of the third NMOS is coupled to the connection terminal; wherein the fourth terminal is coupled to the sub-output terminal. ### Claim 15 (depends on 8) The output stage of claim 8, wherein the driving circuit comprises a differential input differential output amplifier. ### Claim 16 (depends on 15) The output stage of claim 15, wherein the driving circuit comprises a first N type Metal Oxide Semiconductor (NMOS), a second NMOS and a third NMOS, the first NMOS and the second NMOS constitute an input pair, and the third NMOS is arranged to be a current source connected between source terminals of the first NMOS and the second NMOS. ### Claim 17 (depends on 16) The output stage of claim 16, wherein the driving circuit comprises a first resistor and a second resistor, the first resistor is coupled between a first reference voltage and a drain terminal of the first NMOS, and the second resistor is coupled between the first reference voltage and a drain terminal of the second NMOS. ### Claim 18 A semiconductor device, comprising: an output stage, including: a multiplexing circuit, including: a first type transistor; a second type transistor, coupled to the first type transistor, wherein the first type transistor is different from the second type transistor; and an impedance circuit, arranged to provide an impedance between a gate terminal of the first type transistor and the second type transistor; an input circuit arranged to receive a first clock signal and a second clock signal, including a sub-output terminal, and the sub-output terminal is connected to a gate terminal of the second type transistor; and a driving circuit, coupled to the multiplexing circuit; and an output port, coupled to the driving circuit and configured to receive a transmission line. ### Claim 19 (depends on 18) The semiconductor device of claim 18, wherein the impedance circuit includes a resistor, and a terminal of the resistor is connected to the gate terminal of the first type transistor while another terminal of the resistor is connected to an output terminal of the multiplexing circuit. ### Claim 20 (depends on 18) The semiconductor device of claim 18, wherein the multiplexing circuit is free from coupling a passive inductor to an output terminal thereof.