# US 12,191,847 B2 · Method and system of operating a gate driver

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- Number: US 12,191,847 B2
- Document ID: US12191847B2
- Status: Granted
- Kind: B2
- Application number: 18/301,952
- Filed: 2023-04-17
- Published: 2024-10-17
- Granted: 2025-01-07
- Earliest claimed: 2023-04-17
- Assignees: Semiconductor Components Industries, LLC
- Applicants: Semiconductor Components Industries, LLC
- Inventors: Karel Ptacek; Jaroslav Knop
- Web page: https://patentgrep.com/patent/US12191847B2

## CPC

- H03K 17/0822: {in field-effect transistor switches}
- H02M 1/0012: {Control circuits using digital or numerical techniques (in DC/DC converters H02M3/157, H02M3/33515; in DC-AC converters H02M7/53873)}
- H02M 1/0048: {Circuits or arrangements for reducing losses (using snubbers H02M1/34)}
- H02M 1/08: Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M 1/32: Means for protecting converters other than automatic disconnection
- H02M 1/38: Means for preventing simultaneous conduction of switches
- H02M 3/01: {Resonant DC/DC converters}
- H02M 3/33523: {with galvanic isolation between input and output of both the power stage and the feedback loop}
- H02M 3/33571: {Half-bridge at primary side of an isolation transformer}
- H02M 7/537: using semiconductor devices only, e.g. single switched pulse inverters
- H03K 2217/0063: High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load
- H03K 2217/0072: Low side switches, i.e. the lower potential [DC] or neutral wire [AC] being directly connected to the switch and not via the load
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)

## Abstract

Operating a gate driver. At least one example is a method of operating the gate driver, the method comprising: de-asserting a drive-low terminal of the gate driver; starting a single timer within the gate driver; and after expiration of the single timer asserting a drive-high terminal of the gate driver responsive to assertion of an in-high terminal of the gate driver; and then de-asserting the drive-high terminal; starting the single timer; and after a second expiration of the single timer asserting the drive-low terminal responsive to assertion of an in-low terminal of the gate driver.

## Claims

### Claim 1

A method of operating a gate driver, the method comprising:
de-asserting a drive-low terminal of the gate driver;
starting a single timer within the gate driver; and after expiration of the single timer
asserting a drive-high terminal of the gate driver responsive to assertion of an in-high terminal of the gate driver; and then
de-asserting the drive-high terminal;
starting the single timer; and after a second expiration of the single timer
asserting the drive-low terminal responsive to assertion of an in-low terminal of the gate driver.

### Claim 2 (depends on 1)

The method of claim 1:
wherein each starting the single timer comprises charging a capacitor by way of a current source; and
wherein expiration of the single timer comprises a voltage on the capacitor meeting or exceeding a predetermined voltage.

### Claim 3 (depends on 1)

The method of claim 1 further comprising implementing, by the gate driver, a state machine having at least four states:
a first state in which the drive-high terminal is asserted and a timer-start input of the single timer is de-asserted;
a second state in which the drive-high terminal is de-asserted and the timer-start input is asserted starting the single timer, the state machine transitions from the first state to the second state based on de-assertion of the in-high terminal;
a third state in which the drive-low terminal is asserted and the timer-start input is de-asserted, the state machine transitions from the second state to the third state based on assertion of the in-low terminal and assertion of a timer-end output;
a fourth state in which the drive-low terminal is de-asserted and the timer-start input is asserted, the state machine transitions from the third state to the fourth state based on de-assertion of the in-low terminal; and
wherein the state machine transitions from the fourth state to the first state based on assertion of the in-high terminal and assertion of the timer-end output.

### Claim 4 (depends on 3)

The method of claim 3 wherein the state machine transitions from the first state to the second state based on de-assertion of the in-high terminal and de-assertion of the timer-end output.

### Claim 5 (depends on 3)

The method of claim 3 wherein the state machine transitions from the third state to the fourth state based on de-assertion of the in-low terminal and de-assertion of the timer-end output.

### Claim 6

A gate driver, comprising:
an in-high terminal, an in-low terminal, a drive-high terminal, and a drive-low terminal;
a high-side amplifier defining a drive output coupled to the drive-high terminal, and a drive input;
a low-side amplifier defining a drive output coupled to the drive-low terminal, and a drive input;
a timer defining a timer-start input, and a timer-end output;
a controller coupled to the in-high terminal, the in-low terminal, the drive input of the high-side amplifier, the drive input of the low-side amplifier, the timer-start input, and the timer-end output, the controller configured to:
insert a first delay time between de-assertion of the drive-high terminal and assertion of the drive-low terminal, the insertion of the first delay time based on the timer-end output; and
insert a second delay time between de-assertion of the drive-low terminal and assertion of the drive-high terminal, the insertion of the second delay time based on the timer-end output.

### Claim 7 (depends on 6)

The gate driver of claim 6:
wherein when the controller inserts the first delay time, the controller is configured to de-assert the drive-high terminal, assert the timer-start input, and then assert the drive-low terminal upon assertion of the timer-end output; and
wherein when the controller inserts the second delay time, the controller is configured to de-assert the drive-low terminal, assert the timer-start input, and then assert the drive-high terminal upon assertion of the timer-end output.

### Claim 8 (depends on 6)

The gate driver of claim 6 wherein the controller further comprises a state machine having at least four states:
a first state in which the drive-high terminal is asserted and the timer-start input is de-asserted;
a second state in which the drive-high terminal is de-asserted and the timer-start input is asserted, the controller transitions from the first state to the second state based on de-assertion of the in-high terminal;
a third state in which the drive-low terminal is asserted and the timer-start input is de-asserted, the controller transitions from the second state to the third state based on assertion of the in-low terminal and assertion of the timer-end output;
a fourth state in which the drive-low terminal is de-asserted and the timer-start input is asserted, the controller transitions from the third state to the fourth state based on de-assertion of the in-low terminal; and
wherein the controller transitions from the fourth state to the first state based on assertion of the in-high terminal and assertion of the timer-end output.

### Claim 9 (depends on 8)

The gate driver of claim 8 wherein the controller further comprises a fifth state, the controller transitions to the fifth state upon detection of an under-voltage event.

### Claim 10 (depends on 8)

The gate driver of claim 8 wherein the controller transitions from the first state to the second state based on de-assertion of the in-high terminal and de-assertion of the timer-end output.

### Claim 11 (depends on 8)

The gate driver of claim 8 wherein the controller transitions from the third state to the fourth state based on de-assertion of the in-low terminal and de-assertion of the timer-end output.

### Claim 12 (depends on 6)

The gate driver of claim 6 wherein the timer comprises:
a current source defining a current output;
a capacitor defining a first lead coupled to the current output, and a second lead coupled to a reference voltage;
an electrically-controlled switch defining a first lead coupled to the first lead of the capacitor, a second lead coupled to the second lead of the capacitor, and a control input defining the timer-start input; and
a buffer defining a buffer input coupled to the first lead of the capacitor, and a buffer output defining the timer-end output.

### Claim 13

A power converter comprising:
a high-side FET defining a drain coupled to a voltage input, a source defining a switch node, and a gate;
a low-side FET defining a drain coupled to the switch node, a source coupled to a reference voltage, and a gate;
an inductance coupled to the switch node;
a rectifier coupled to the inductance;
a gate driver defining an in-high terminal, an in-low terminal, a drive-high terminal coupled to the gate of the high-side FET, and a drive-low terminal coupled to the gate of the low-side FET;
a converter controller coupled to the in-high terminal and the in-low terminal, the converter controller configured to alternately assert the in-high terminal and the in-low terminal;
the gate driver configured to:
insert a first delay time between de-assertion of the drive-high terminal and assertion of the drive-low terminal based on a timer within the gate driver, and
insert a second delay time between de-assertion of the drive-low terminal and assertion of the drive-high terminal based on the timer.

### Claim 14 (depends on 13)

The power converter of claim 13:
wherein when the gate driver inserts the first delay time, the gate driver is configured to de-assert the drive-high terminal, start the timer, and then assert the drive-low terminal upon assertion of a timer-end output; and
wherein when the gate driver inserts the second delay time, the gate driver is configured to de-assert the drive-low terminal, start the timer, and then assert the drive-high terminal upon assertion of the timer-end output.

### Claim 15 (depends on 13)

The power converter of claim 13 wherein the timer comprises:
a current source defining a current output;
a capacitor defining a first lead coupled to the current output, and a second lead coupled to a reference voltage;
an electrically-controlled switch defining a first lead coupled to the first lead of the capacitor, a second lead coupled to the second lead of the capacitor, and a control input defining a timer-start input; and
a buffer defining a buffer input coupled to the first lead of the capacitor, and a buffer output defining a timer-end output.

### Claim 16 (depends on 13)

The power converter of claim 13 wherein the gate driver further comprises a state machine having at least four states:
a first state in which the drive-high terminal is asserted and a timer-start input is de-asserted;
a second state in which the drive-high terminal is de-asserted and the timer-start input is asserted, the gate driver transitions from the first state to the second state based on de-assertion of the in-high terminal;
a third state in which the drive-low terminal is asserted and the timer-start input is de-asserted, the gate driver transitions from the second state to the third state based on assertion of the in-low terminal and assertion of a timer-end output;
a fourth state in which the drive-low terminal is de-asserted and the timer-start input is asserted, the gate driver transitions from the third state to the fourth state based on de-assertion of the in-low terminal; and
wherein the gate driver transitions from the fourth state to the first state based on assertion of the in-high terminal and assertion of a timer-end output.

### Claim 17 (depends on 16)

The power converter of claim 16 wherein the gate driver transitions from the first state to the second state based on de-assertion of the in-high terminal and de-assertion of the timer-end output.

### Claim 18 (depends on 16)

The power converter of claim 16 wherein the gate driver transitions from the third state to the fourth state based on de-assertion of the in-low terminal and de-assertion of the timer-end output.

### Claim 19 (depends on 13)

The power converter of claim 13 wherein the inductance is an inductor having a first lead coupled to the switch node, and a second lead coupled to the rectifier.

### Claim 20 (depends on 13)

The power converter of claim 13 wherein the inductance is a transformer having a primary winding coupled to the switch node, and a secondary winding coupled to the rectifier.