Compact single stage wideband power amplifier

A method for improving the stability, gain, flatness and return loss and reducing the size of a power amplifier, comprising:

• a) providing a two-stage power amplifier in balanced cascode FET-based topology that consists of:
• a.1) a first common-source stage feeding into a first common-gate (CG) stage;
• a.2) a second common-source stage feeding into a second common-gate (CG) stage;
• a.3) an input matching network for matching the input impedance of said a two-stage power amplifier to a desired signal source impedance;
• a.4) an output matching network for matching the output impedance of said a two-stage power amplifier to a desired load;
• b) adding a first positive feedback path between the gate of the first common-source stage and the drain of the second common-gate (CG) stage and a second positive feedback path between the gate of the second common-source stage and the drain of the first common-gate (CG) stage;
• c) adding a first negative feedback path between the drain of the first common-gate (CG) stage and the gate of the first common-source stage and a second negative feedback path between the drain of the second common-gate (CG) stage and the gate of the second common-source stage;
• d) adding a first inter-stage matching network between the first common-source (CS) stage and the first common-gate (CG) stage;
• and
• e) adding a second inter-stage matching network between the second common-source (CS) stage and the second common-gate (CG) stage.