# US 12,191,810 B2 · Multi-resonant oscillator/clock

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- Number: US 12,191,810 B2
- Document ID: US12191810B2
- Status: Granted
- Kind: B2
- Application number: 18/507,973
- Filed: 2023-11-13
- Published: 2024-04-11
- Granted: 2025-01-07
- Earliest claimed: 2022-09-29
- Assignees: Analog Bits Inc.
- Applicants: Analog Bits Inc.
- Inventors: Michael A. Ang; Alan C. Rogers
- Web page: https://patentgrep.com/patent/US12191810B2

## CPC

- H03B 5/1228: {the amplifier comprising one or more field effect transistors}
- H03B 5/1212: {the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair}
- H03B 5/1243: {the means comprising voltage variable capacitance diodes}
- H03B: GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS (generators adapted for electrophonic musical instruments G10H; masers or lasers H01S; generation of oscillations in plasma H05H)

## Abstract

A clock device including: an LC network comprising: a first inductive portion; a second inductive portion connected to the first inductive portion; a third inductive portion connected to the second inductive portion; a first capacitive portion connected to the first, the second, and the third inductive portions; and a second capacitive portion connected to the first inductive portion and the third inductive portion, wherein the LC network is configured to simultaneously resonate at a first frequency and a second frequency that is substantially three times the first frequency, and wherein the clock signal is provided between the first and the third inductive portions by combining a first signal component and a second signal component that is a third harmonic of the first signal component and each inflection point of the first signal component is phase aligned with a corresponding inflection point of the second signal component.

## Claims

### Claim 1

A method to generate a clock signal using a clock device, the method comprises:
configuring an LC network on the clock device as a multi-resonance network that simultaneously resonates at a first resonance frequency and a second resonance frequency that is substantially three times the first resonance frequency;
synthesizing the clock signal by a combination of a first resonating signal component at the first resonance frequency and a second resonating signal component at the second resonance frequency, wherein each inflection point of the first resonating signal component is phase aligned with a corresponding inflection point of the second resonating signal component; and
directly driving, using the clock signal, a load coupled to the clock device.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
simultaneously operating on the first resonating signal and the second resonating signal, using a gain stage on the clock device, such that a ratio of the second resonance frequency over the first resonance frequency is maintained.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
installing, on the gain stage, a complementary metaloxide semiconductor (CMOS) amplifier that comprises a first pair of complementary transistors and a second pair of complementary transistors;
arranging an output node of the first pair of complementary transistors as separately AC-coupled to input gates of the second pair of complementary transistors; and
arranging an output node of the second pair of complementary transistors as separately AC-coupled to input gates of the first pair of complementary transistors; and
setting input gates of the first pair of complementary transistors to receive respective bias voltages; and
setting input gates of the second pair of complementary transistors to receive the respective bias voltages.

### Claim 4 (depends on 1)

The method of claim 1, wherein the load comprises a CMOS gate load.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
configuring the LC network to include a first inductive portion, a second inductive portion, a third inductive portion, a first capacitive portion, and a second capacitive portion;
connecting a first terminal of the second inductive portion to a second terminal of the first inductive portion;
connecting a first terminal of the third inductive portion to a second terminal of the second inductive portion;
connecting a first terminal of the first capacitive portion to the second terminal of the first inductive portion and the first terminal of the second inductive portion;
connecting a second terminal of the first capacitive portion to the second terminal of the second inductive portion and the first terminal of the third inductive portion;
connecting a first terminal of the second capacitive portion to the first terminal of the first inductive portion; and
connecting a second terminal of the second capacitive portion to the second terminal of the third inductive portion.

### Claim 6 (depends on 5)

The method of claim 5, further comprising:
tuning the clock device over a range of frequencies.

### Claim 7 (depends on 6)

The method of claim 6, wherein said tuning comprises:
varying a capacitance Cp that characterizes the first capacitive portion and a capacitance Cs that characterizes the second capacitive portion while substantially fixing a ratio of Cp/Cs.

### Claim 8 (depends on 7)

The method of claim 7, wherein the first inductive portion is characterized by an inductance of Ls/2,
wherein the second inductive portion is characterized by an inductance of Lp,
wherein the third inductive portion is characterized by an inductance of Ls/2, and
wherein the first resonance frequency is characterized by:
f
1
=
1
2
⁢
π
⁢
(
L
s
⁢
C
s
+
L
p
⁢
C
s
+
L
p
⁢
C
p
)
-
(
L
s
⁢
C
s
+
L
p
⁢
C
s
+
L
p
⁢
C
p
)
2
-
4
*
L
s
⁢
L
p
⁢
C
s
⁢
C
p
2
*
L
s
⁢
L
p
⁢
C
s
⁢
C
p
,
wherein the second resonance frequency is characterized by:
f
2
=
1
2
⁢
π
⁢
(
L
s
⁢
C
s
+
L
p
⁢
C
s
+
L
p
⁢
C
p
)
+
(
L
s
⁢
C
s
+
L
p
⁢
C
s
+
L
p
⁢
C
p
)
2
-
4
*
L
s
⁢
L
p
⁢
C
s
⁢
C
p
2
*
L
s
⁢
L
p
⁢
C
s
⁢
C
p
.

### Claim 9 (depends on 5)

The method of claim 5, further comprising:
coupling the first terminal of the first inductive portion to a first chip capacitor load; and
coupling the second terminal of the third inductive portion to a second chip capacitor load,
wherein the first chip capacitor load and the second chip capacitor load are coupled to a semiconductor chip or sub-components thereof.

### Claim 10 (depends on 9)

The method of claim 9, wherein the semiconductor chip comprises a CMOS system on chip (SOC) device.