# US 12,191,808 B1 · Transformer-based distributed multicore oscillator and integrated circuit and terminal thereof

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- Number: US 12,191,808 B1
- Document ID: US12191808B1
- Status: Granted
- Kind: B1
- Application number: 18/828,071
- Filed: 2024-09-09
- Published: 2024-12-26
- Granted: 2025-01-07
- Earliest claimed: 2022-03-11
- Assignees: Anhui Transilica Microelectronics Co., Ltd.
- Applicants: Anhui Transilica Microelectronics Co., Ltd.
- Inventors: Yizhe Hu; Fujiang Lin
- Web page: https://patentgrep.com/patent/US12191808B1

## CPC

- H03B 5/1212: {the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair}
- H03B 5/1296: {the feedback circuit comprising a transformer}
- H03B 5/1852: {the semiconductor device being a field-effect device}
- H03B 2200/0024: including parallel striplines
- Y02D 30/70: in wireless communication networks
- H03B: GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS (generators adapted for electrophonic musical instruments G10H; masers or lasers H01S; generation of oscillations in plasma H05H)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

The present invention belongs to the field of radio frequency integrated circuit technology, and specifically relates to a transformer-based distributed multicore oscillator and an integrated circuit and a terminal thereof. The oscillator includes four MOS transistors M1˜M4, two transformers T1 and T2, two coarse capacitors arrays CG1 and CG2, two fine capacitors arrays CD1 and CD2, two tail inductances Ltail1 and Ltail2. A first cross-coupled transistors pair is constisted by two MOS transistors M1 and M2, and a second cross-coupled transistors pair is constisted by two MOS transistors M3 and M4. Two pair are adjacent and are set in centre of the layout. Two signal output ports are defined by two drain regions of any two MOS transistors from the two pairs. The present invention synchronously solves the problem of high thermal phase noise and low-frequency flicker phase noise in existing oscillators.

## Claims

### Claim 1

A transformer-based distributed multicore oscillator, used as a millimeter wave oscillator, comprises: four MOS transistors M1˜M4, two transformers T1 and T2, two coarse capacitors arrays CG1 and CG2, two fine capacitors arrays
CD1 and CD2, two tail inductances Ltail1 and Ltail2;
wherein a first cross-coupled transistors pair is constisted by two MOS transistors M1 and M2, a second cross-coupled transistors pair is constisted by two MOS transistors M3 and M4; the two transformers T1 and T2 are set symmetrically with two inner coils Ld being defined inside and two outer coils Lg being defined outside; the two transformers T1 and T2 have the same construction and the same turns ratio of 1:1 between the inner coil Ld and the outer coil Lg; the inner coil Ld of the transformer T1, the fine capacitors array CD1, the inner coil Ld of the transformer T2, the fine capacitors array CD2 are connected in series successively; the outer coil Lg of the transformer T1, the coarse capacitors array CG1, the outer coil Lg of the transformer T2, the coarse capacitors array CG2 are connected in series successively; the two inner coils Ld are cross-linked; two drain regions of two MOS transistors M1 and M2 are connected with two ends of the fine capacitors array CD1 respectively, two drain regions of two MOS transistors M3 and M4 are connected with two ends of the fine capacitors array CD2 respectively; two grid regions of two MOS transistors M1 and M2 are connected with two ends of the coarse capacitors array CG1 respectively, two grid regions of two MOS transistors M3 and M4 are connected with two ends of the coarse capacitors array CG2 respectively; two source regions of two MOS transistors M1 and M3 are both connected to a ground Vss via the tail inductances Ltail1, two source regions of two MOS transistors M2 and M4 are both connected to the ground Vss via the tail inductances Ltail2; taps of the two transformers T1 and T2 are connected with a voltage source Vdd;
two signal output ports are defined by two drain regions of any two MOS transistors from the two cross-coupled transistors pairs;
the layout of the oscillator is designed as follows:
a cross-coupled unit being defined by the two cross-coupled transistors pairs, and the two cross-coupled transistors pairs being adjacent and being set in centre of the layout;
the two transformers T1 and T2 being set on the periphery of the cross-coupled unit;
all capacitors arrays being set on the periphery of the cross-coupled unit, and the coarse capacitors arrays being outerside, the fine capacitors arrays being inside;
a NT_N layer being arranged in a annular region distributed by the two transformers T1 and T2; the cross-coupled unit being located inside of the annular region and being out of touch with the NT_N layer; all capacitors arrays being located outside of the annular region.

### Claim 2 (depends on 1)

The oscillator according to claim 1, wherein each capacitors array of CG1, CG2, CD1 and CD2 comprises a plurality of switched capacitors which are in parallel, and each switched capacitor is a adjustable capacitor.

### Claim 3 (depends on 2)

The oscillator according to claim 2, wherein the two coarse capacitors arrays CG1 and CG2 have the same specifications and parameters; the two fine capacitors arrays CD1 and CD2 have the same specifications and parameters; the capacitances of the adjustable capacitors are changed synchronously for getting right frequency of the output of the oscillator.

### Claim 4 (depends on 3)

The oscillator according to claim 3, wherein capacitors in the coarse capacitors array are gate capacitances, and capacitors in the fine capacitors array are source capacitances; the ratio of capacitance value between the gate capacitance and the source capacitance is 2˜4.

### Claim 5 (depends on 3)

The oscillator according to claim 3, wherein a capacitor defined as a decoupling capacitor is electrically connected between the ground Vss and the voltage source Vdd.

### Claim 6 (depends on 1)

An integrated circuit, comprises a transformer-based distributed multicore oscillator according to claim 1;
wherein in the layout of the integrated circuit, the oscillator is further designed as follows:
(1) in the cross-coupled unit, the four MOS transistors M1˜M4 being located at the four corners of a rectangular area one by one; any two adjacent MOS transistors being symmetric;
(2) the two transformers T1 and T2 being symmetrical; the two inner coils Ld being cross-linked;
(3) the fine capacitors array CD1 and the coarse capacitors array CG1 being close to the first cross-coupled transistors pair, the fine capacitors array CD2 and the coarse capacitors array CG2 being close to the second cross-coupled transistors pair;
(4) two voltage sources Vdd and two grounds Vss being arranged outside of the cross-coupled unit, a first group defined by one voltage source Vdd and one ground Vss being close to the two MOS transistors M1 and M3, a second group defined by another voltage source Vdd and another ground Vss being close to the two MOS transistors M2 and M4; the two groups having a shortest physical distance.

### Claim 7 (depends on 6)

The integrated circuit according to claim 6, wherein a full-differential capacitors array is defined by the two coarse capacitors arrays and the two fine capacitors arrays; the tail inductance Ltail1 is electrically connected between the ground Vss and the two source regions of the two MOS transistors M1 and M3, the tail inductance Ltail2 is electrically connected between the ground Vss and the two source regions of the two MOS transistors M2 and M4; the two tail inductances Ltail1 and Ltail2 run form the annular region without of touch with the NT_N layer to be below of the voltage source Vdd; a decoupling capacitor is connected between the voltage source Vdd and the ground Vss.

### Claim 8 (depends on 6)

The integrated circuit according to claim 6, wherein each capacitors array of CG1, CG2, CD1 and CD2 comprises a plurality of switched capacitors which are in parallel, and each switched capacitor is a adjustable capacitor.

### Claim 9 (depends on 8)

The integrated circuit according to claim 8, wherein the two coarse capacitors arrays CG1 and CG2 have the same specifications and parameters; the two fine capacitors arrays CD1 and CD2 have the same specifications and parameters; the capacitances of the adjustable capacitors are changed synchronously for getting right frequency of the output of the oscillator.

### Claim 10 (depends on 9)

The integrated circuit according to claim 9, wherein capacitors in the coarse capacitors array are gate capacitances, and capacitors in the fine capacitors array are source capacitances; the ratio of capacitance value between the gate capacitance and the source capacitance is 2˜4.

### Claim 11 (depends on 9)

The integrated circuit according to claim 9, wherein a capacitor defined as a decoupling capacitor is electrically connected between the ground Vss and the voltage source Vdd.

### Claim 12 (depends on 6)

A terminal, comprises:
an RF frequency device;
a integrated circuit according to claim 6, used to provide a local carrier signal for the RF device.

### Claim 13 (depends on 12)

The terminal according to claim 12, wherein a full-differential capacitors array is defined by the two coarse capacitors arrays and the two fine capacitors arrays; the tail inductance Ltail1 is electrically connected between the ground Vss and the two source regions of the two MOS transistors M1 and M3, the tail inductance Ltail2 is electrically connected between the ground Vss and the two source regions of the two MOS transistors M2 and M4; the two tail inductances Ltail1 and Ltail2 run form the annular region without of touch with the NT_N layer to be below of the voltage source Vdd; a decoupling capacitor is connected between the voltage source Vdd and the ground Vss.

### Claim 14 (depends on 12)

The terminal according to claim 12, wherein each capacitors array of CG1, CG2, CD1 and CD2 comprises a plurality of switched capacitors which are in parallel, and each switched capacitor is a adjustable capacitor.

### Claim 15 (depends on 14)

The terminal according to claim 14, wherein the two coarse capacitors arrays CG1 and CG2 have the same specifications and parameters; the two fine capacitors arrays CD1 and CD2 have the same specifications and parameters; the capacitances of the adjustable capacitors are changed synchronously for getting right frequency of the output of the oscillator.

### Claim 16 (depends on 15)

The terminal according to claim 15, wherein capacitors in the coarse capacitors array are gate capacitances, and capacitors in the fine capacitors array are source capacitances; the ratio of capacitance value between the gate capacitance and the source capacitance is 2˜4.

### Claim 17 (depends on 15)

The terminal according to claim 15, wherein a capacitor defined as a decoupling capacitor is electrically connected between the ground Vss and the voltage source Vdd.